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`protect end_protected
| bsd-3-clause |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_16/hdl/xbip_utils_v3_0_vh_rfs.vhd | 13 | 163693 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 119040)
`protect data_block
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`protect end_protected
| bsd-3-clause |
GustaMagik/RSA_Security_Token | VHDL_code/ver_A/RSA_Security_Token_Keyboard_Version/ModMult.vhd | 1 | 6187 | ----------------------------------------------------------------------
---- ----
---- Modular Multiplier ----
---- RSA Public Key Cryptography IP Core ----
---- ----
---- This file is part of the BasicRSA project ----
---- http://www.opencores.org/ ----
---- ----
---- To Do: ----
---- - Speed and efficiency improvements ----
---- - Possible revisions for good engineering/coding practices ----
---- ----
---- Author(s): ----
---- - Steven R. McQueen, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2003 Steven R. McQueen ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
-- This module implements the modular multiplier for the RSA Public Key Cypher. It expects
-- to receive a multiplicand on th MPAND bus, a multiplier on the MPLIER bus, and a modulus
-- on the MODULUS bus. The multiplier and multiplicand must have a value less than the modulus.
--
-- A Shift-and-Add algorithm is used in this module. For each bit of the multiplier, the
-- multiplicand value is shifted. For each '1' bit of the multiplier, the shifted multiplicand
-- value is added to the product. To ensure that the product is always expressed as a remainder
-- two subtractions are performed on the product, P2 = P1-modulus, and P3 = P1-(2*modulus).
-- The high-order bits of these results are used to determine whether P sould be copied from
-- P1, P2, or P3.
--
-- The operation ends when all '1' bits in the multiplier have been used.
--
-- Comments, questions and suggestions may be directed to the author at [email protected].
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity modmult is
Generic (MPWID: integer := 72);
Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
mplier : in std_logic_vector(MPWID-1 downto 0);
modulus : in std_logic_vector(MPWID-1 downto 0);
product : out std_logic_vector(MPWID-1 downto 0);
clk : in std_logic;
ds : in std_logic;
reset : in std_logic;
ready : out std_logic);
end modmult;
architecture modmult1 of modmult is
signal mpreg: std_logic_vector(MPWID-1 downto 0);
signal mcreg, mcreg1, mcreg2: std_logic_vector(MPWID+1 downto 0);
signal modreg1, modreg2: std_logic_vector(MPWID+1 downto 0);
signal prodreg, prodreg1, prodreg2, prodreg3, prodreg4: std_logic_vector(MPWID+1 downto 0);
--signal count: integer;
signal modstate: std_logic_vector(1 downto 0);
signal first: std_logic;
begin
-- final result...
product <= prodreg4(MPWID-1 downto 0);
-- add shifted value if place bit is '1', copy original if place bit is '0'
with mpreg(0) select
prodreg1 <= prodreg + mcreg when '1',
prodreg when others;
-- subtract modulus and subtract modulus * 2.
prodreg2 <= prodreg1 - modreg1;
prodreg3 <= prodreg1 - modreg2;
-- negative results mean that we subtracted too much...
modstate <= prodreg3(mpwid+1) & prodreg2(mpwid+1);
-- select the correct modular result and copy it....
with modstate select
prodreg4 <= prodreg1 when "11",
prodreg2 when "10",
prodreg3 when others;
-- meanwhile, subtract the modulus from the shifted multiplicand...
mcreg1 <= mcreg - modreg1;
-- select the correct modular value and copy it.
with mcreg1(MPWID) select
mcreg2 <= mcreg when '1',
mcreg1 when others;
ready <= first;
combine: process (clk, first, ds, mpreg, reset) is
begin
if reset = '1' then
first <= '1';
elsif rising_edge(clk) then
if first = '1' then
-- First time through, set up registers to start multiplication procedure
-- Input values are sampled only once
if ds = '1' then
mpreg <= mplier;
mcreg <= "00" & mpand;
modreg1 <= "00" & modulus;
modreg2 <= '0' & modulus & '0';
prodreg <= (others => '0');
first <= '0';
end if;
else
-- when all bits have been shifted out of the multiplicand, operation is over
-- Note: this leads to at least one waste cycle per multiplication
if mpreg = 0 then
first <= '1';
else
-- shift the multiplicand left one bit
mcreg <= mcreg2(MPWID downto 0) & '0';
-- shift the multiplier right one bit
mpreg <= '0' & mpreg(MPWID-1 downto 1);
-- copy intermediate product
prodreg <= prodreg4;
end if;
end if;
end if;
end process combine;
end modmult1;
| bsd-3-clause |
GustaMagik/RSA_Security_Token | VHDL_code/ver_B/RSA_Security_Token_USB_Version/USB_CMD_PARSER.vhd | 1 | 14496 |
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg
--Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--
--1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--
--2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the
--documentation and/or other materials provided with the distribution.
--
--3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this
--software without specific prior written permission.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
--BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
--GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_MISC.all;
use IEEE.NUMERIC_STD.all;
entity USB_CMD_PARSER is
generic ( data_addr_width : integer;
Frequency : integer);
Port ( RXD_BYTE : in STD_LOGIC_VECTOR (7 downto 0); --Input byte from the serial-to-parallell translator
TXD_BYTE : out STD_LOGIC_VECTOR (7 downto 0); --Output byte to the parallell-to-serial translator
RAM_ADDR : out STD_LOGIC_VECTOR (data_addr_width-1 downto 0) := (others => '1'); --RAM ADDR where the RSA (signed) message is
RAM_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); --DATA from the active RAM cell
RAM_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0); --DATA to be written to active RAM cell if WE is high
VALID_DATA_IN : in STD_LOGIC; --Flag to the parallell-to-serial translator to tell it that there's a new byte on the bus
VALID_DATA_OUT : out STD_LOGIC; --Flag from the serial-to-parallell translator to tell that there's a new byte on the bus
RAM_WE : out STD_LOGIC; --RAM Write Enable flag
RSA_DONE : in STD_LOGIC; --Flag from RSA module that the values in RAM are the signed message
READY_FOR_DATA : in STD_LOGIC; --Flag from RSA module that it is ready to recive a new message to sign
RESET : in STD_LOGIC; --Reset for module. When high all registers and counters resets at next high flank of the clock
CLK : in STD_LOGIC; --Global clock signal
DATA_READY : out STD_LOGIC := '0'; --Flag for 64 byte recieved
FIFO_EMPTY : in STD_LOGIC);
end USB_CMD_PARSER;
--USB_CMD_PARSER is a module that recives whole bytes from RXD_Controller and parses them as
--either command or data.
--The commands are all this module accepts, and any other data recieved is disgarded.
--Everything that is to be sent is put in the TXD_FIFO in order of how it should be sent.
--The commands are all on the form '*' followed by the command specific character, and are as follows:
--*I - Request ID. The parser will respond with *IHEJ
--*W[64 byte] - Write request. Depending on READY_FOR_DATA flag, this will either
--respond with *B for "busy" or *D when all 64 bytes has been written to memory
--*R -- Request encrypted data. Depending on DATA_READY flag, this will either
--respond with *B for "busy" or *M[64 bytes], where the 64 bytes are the encrypted data
--In certain cases if data is either not recieved or not provided, the module will respond
--with *T for timeout
architecture Behavioral of USB_CMD_PARSER is
constant ASCII_ASTERISK : STD_LOGIC_VECTOR(7 downto 0) := x"2A"; --*
constant ASCII_B : STD_LOGIC_VECTOR(7 downto 0) := x"42"; --B
constant ASCII_D : STD_LOGIC_VECTOR(7 downto 0) := x"44"; --D
constant ASCII_E : STD_LOGIC_VECTOR(7 downto 0) := x"45"; --E
constant ASCII_H : STD_LOGIC_VECTOR(7 downto 0) := x"48"; --H
constant ASCII_J : STD_LOGIC_VECTOR(7 downto 0) := x"4A"; --J
constant ASCII_W : STD_LOGIC_VECTOR(7 downto 0) := x"57"; --W
constant ASCII_R : STD_LOGIC_VECTOR(7 downto 0) := x"52"; --R
constant ASCII_M : STD_LOGIC_VECTOR(7 downto 0) := x"4D"; --M
constant ASCII_I : STD_LOGIC_VECTOR(7 downto 0) := x"49"; --I
constant ASCII_T : STD_LOGIC_VECTOR(7 downto 0) := x"54"; --T
--No. They are not in alphabetical order. Deal with it
type STATES is (IDLE, TRANSLATE_CMD, DO_CMD); --States for the overarching functionality
type CMDS is (TIMEOUT, RECIVE_DATA, TRANSMIT_DATA, TRANSMIT_ID, TRANSMIT_BUSY); --Depending on flags and inputs different commands are to be executed
signal TIMEOUT_COUNTER : integer range 0 to Frequency/2 := 0;
signal BYTE_COUNTER : unsigned (7 downto 0) := (others => '0'); --Counter to keep track of what byte in memory to read/write
signal HEADER_COUNTER : unsigned (1 downto 0) := (others => '0'); --counter to keep track of if an * or a message specific char is to be sent
signal STATE : STATES := IDLE;
signal CMD : CMDS;
signal flag : std_logic := '0';
Signal DATA_READY_S : STD_LOGIC;
begin
DATA_READY <= DATA_READY_S;
process(clk)
variable RECIVED_DATA : STD_LOGIC_VECTOR(7 downto 0);
--Procedure for IDLE state
procedure IDLE
(DATA : in STD_LOGIC_VECTOR(7 downto 0); --Data form RXD
signal STATE : out STATES) is
begin
if DATA = ASCII_ASTERISK then --Procede iff the header * is detected
state <= TRANSLATE_CMD;
end if;
end IDLE;
--Procedure for TRANSLATE_CMD state
procedure TRANSLATE
(DATA : in STD_LOGIC_VECTOR(7 downto 0); --Data from RXD
signal STATE : out STATES;
signal CMD : out CMDS;
signal RAM_ADDR : out STD_LOGIC_VECTOR(data_addr_width-1 downto 0)) is
begin
case DATA is
--Write request
when ASCII_W =>
STATE <= DO_CMD;
--If ready for recieving data we can execute this command
if READY_FOR_DATA = '1' then
CMD <= RECIVE_DATA;
else --otherwise we have to tell the PC that we're busy
CMD <= TRANSMIT_BUSY;
end if;
--Request of data from the PC
when ASCII_R =>
STATE <= DO_CMD;
--If the RSA is done and in memory, and no other active transmit jobs, we can transmit it to the PC
if RSA_DONE = '1' AND FIFO_EMPTY = '1' then
CMD <= TRANSMIT_DATA;
RAM_ADDR <= (others => '0');
else --Otherwise tell the PC that the unit is busy
CMD <= TRANSMIT_BUSY;
end if;
--Request of ID-sequence from the PC
when ASCII_I =>
STATE <= DO_CMD;
CMD <= TRANSMIT_ID;
--Illegal command. Go back to idle
when others =>
STATE <= IDLE;
end case;
end TRANSLATE;
--Procedure for DO_CMD state
procedure DO_CMD
(DATA : in STD_LOGIC_VECTOR(7 downto 0); --Data form RXD as input
BYTE_COUNT : in unsigned(7 downto 0); --Byte_counter as input
HEADER_COUNT : in unsigned(1 downto 0); --Header_counter as input
CMD : in CMDS; --current CMD as input
VALID_DATA_IN : in STD_LOGIC; --VALID_DATA_IN as input
variable byte_count_var, header_count_var : in integer; --integer versions of the counters as inputs
signal STATE : out STATES; --May change current state
signal RAM_ADDR : out STD_LOGIC_VECTOR(data_addr_width-1 downto 0); --May change RAM_ADDR
signal RAM_WE, VALID_DATA_OUT : out STD_LOGIC; --May change WE and VALID flags
signal RAM_DATA_OUT, TXD_BYTE : out STD_LOGIC_VECTOR (7 downto 0);--May change RAM_DATA_OUT and TXD
signal BYTE_COUNTER : out unsigned(7 downto 0); --May change the counters
signal HEADER_COUNTER : out unsigned(1 downto 0)) is
begin
case CMD is
--Recieve data case. Write the following 64 bytes to the RAM
when RECIVE_DATA =>
if BYTE_COUNT_var > 63 then --all bytes have been written
RAM_ADDR <= (others => '1'); --Reset signals that are not used anymore
RAM_WE <= '0';
RAM_DATA_OUT <= (others => '0');
VALID_DATA_OUT <= '1';
DATA_READY_S <= '1';
if header_count_var = 0 then -- When the message is recived, tell the PC by sending *D
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
TXD_BYTE <= ASCII_D;
HEADER_COUNTER <= (others => '0');
STATE <= IDLE;
BYTE_COUNTER <= (others => '0');
end if;
elsif VALID_DATA_IN = '1' then --Write the current number to the current cell in memory
DATA_READY_S <= '0';
RAM_ADDR <= STD_LOGIC_VECTOR(BYTE_COUNT(5 downto 0));
RAM_DATA_OUT <= DATA;
RAM_WE <= '1';
BYTE_COUNTER <= BYTE_COUNT + 1; --inc the RAM ptr
end if;
--Tansmit data case. Write the first 64 bytes in RAM to the port
when TRANSMIT_DATA =>
VALID_DATA_OUT <= '1';
--First write the header *M for signal to the PC that a message is comming
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
elsif HEADER_COUNT_var = 1 then
TXD_BYTE <= ASCII_M;
HEADER_COUNTER <= HEADER_COUNT + 1;
BYTE_COUNTER <= BYTE_COUNT + 1;
elsif BYTE_COUNT_VAR > 63 then --all bytes has been transmitted
STATE <= IDLE;
RAM_ADDR <= (others => '0');
BYTE_COUNTER <= (others => '0');
TXD_BYTE <= RAM_DATA_IN;
else --Put the data to the serial out
RAM_ADDR <= STD_LOGIC_VECTOR(BYTE_COUNT(5 downto 0));
TXD_BYTE <= RAM_DATA_IN;
BYTE_COUNTER <= BYTE_COUNT + 1;
end if;
when TRANSMIT_ID =>
--First write the header *I for signal to the PC that an ID is comming
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
elsif HEADER_COUNT_var = 1 then
TXD_BYTE <= ASCII_I;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
--Put the ID on the serial out. The ID is: HEJ
case BYTE_COUNT_VAR is
when 0 =>
TXD_BYTE <= ASCII_H;
BYTE_COUNTER <= BYTE_COUNT + 1;
when 1 =>
TXD_BYTE <= ASCII_E;
BYTE_COUNTER <= BYTE_COUNT + 1;
when others =>
TXD_BYTE <= ASCII_J; --Last char to be transmitted. Return to IDLE state
STATE <= IDLE;
HEADER_COUNTER <= (others => '0');
BYTE_COUNTER <= (others => '0');
end case;
end if;
VALID_DATA_OUT <= '1';
when TRANSMIT_BUSY =>
--First write the header *B for signal to tell PC that unit is busy
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
TXD_BYTE <= ASCII_B;
HEADER_COUNTER <= (others => '0');
STATE <= IDLE;
end if;
VALID_DATA_OUT <= '1';
when TIMEOUT =>
RAM_ADDR <= (others => '1'); --Reset signals that are not used anymore
RAM_WE <= '0';
RAM_DATA_OUT <= (others => '0');
VALID_DATA_OUT <= '1';
BYTE_COUNTER <= (others => '0');
if HEADER_COUNT_var = 0 then
TXD_BYTE <= ASCII_ASTERISK;
HEADER_COUNTER <= HEADER_COUNT + 1;
else
TXD_BYTE <= ASCII_T;
HEADER_COUNTER <= (others => '0');
STATE <= IDLE;
end if;
end case;
end DO_CMD;
variable BYTE_COUNT_VAR : integer := 0;
variable HEADER_COUNT_VAR : integer := 0;
begin
if rising_edge(clk) then
if RESET = '1' then --synchronous reset
STATE <= IDLE;
-- CMD <= NONE;
VALID_DATA_OUT <= '0';
RAM_ADDR <= (others => '0');
RAM_DATA_OUT <= (others => '0');
RAM_WE <= '0';
TXD_BYTE <= (others => '0');
BYTE_COUNTER <= (others => '0');
HEADER_COUNTER <= (others => '0');
TIMEOUT_COUNTER <= 0;
DATA_READY_S <= '0';
else
if DATA_READY_S = '1' and READY_FOR_DATA = '1' then
DATA_READY_S <= '0';
end if;
case STATE is
when IDLE => --Reset everything
VALID_DATA_OUT <= '0';
RAM_ADDR <= (others => '0');
RAM_DATA_OUT <= (others => '0');
RAM_WE <= '0';
TXD_BYTE <= (others => '0');
BYTE_COUNTER <= (others => '0');
HEADER_COUNTER <= (others => '0');
TIMEOUT_COUNTER <= 0;
--If we have a valid input and that input is * then we are going to the TRANSLATE_CMD state
if VALID_DATA_IN = '1' then
RECIVED_DATA := RXD_BYTE; --create variable for procedure
--Use the procedure IDLE with the signals and variables that it desires
IDLE(RECIVED_DATA, STATE);
end if;
--Parse the command
when TRANSLATE_CMD =>
--Timeout counter
if TIMEOUT_COUNTER < Frequency/2-1 then --If not timeout yet, increase the counter
TIMEOUT_COUNTER <= TIMEOUT_COUNTER + 1;
end if;
if VALID_DATA_IN = '1' then
RECIVED_DATA := RXD_BYTE; --create variable for procedure
--Use the procedure TRANSLATE with the signals and variables that it desires
TRANSLATE(RECIVED_DATA, STATE, CMD, RAM_ADDR);
TIMEOUT_COUNTER <= 0;
elsif TIMEOUT_COUNTER >= Frequency/2-1 then
STATE <= DO_CMD;
CMD <= TIMEOUT;
TIMEOUT_COUNTER <= 0;
end if;
--Do the command that was decided from TRANSLATE
when DO_CMD =>
RECIVED_DATA := RXD_BYTE;
BYTE_COUNT_VAR := to_integer(BYTE_COUNTER); --create variables for procedure
HEADER_COUNT_VAR := to_integer(HEADER_COUNTER);
--Use the procedure DO_CMD with the signals and variables that it desires unless timeout
DO_CMD(DATA => RECIVED_DATA,
BYTE_COUNT => BYTE_COUNTER,
HEADER_COUNT => HEADER_COUNTER,
CMD => CMD,
VALID_DATA_IN => VALID_DATA_IN,
BYTE_COUNT_VAR => BYTE_COUNT_VAR,
HEADER_COUNT_VAR => HEADER_COUNT_VAR, --inputs
STATE => STATE,
RAM_ADDR => RAM_ADDR,
RAM_WE => RAM_WE,
VALID_DATA_OUT => VALID_DATA_OUT,
RAM_DATA_OUT => RAM_DATA_OUT,
TXD_BYTE => TXD_BYTE,
BYTE_COUNTER => BYTE_COUNTER,
HEADER_COUNTER => HEADER_COUNTER); --outputs
--Timeout counter
if TIMEOUT_COUNTER < Frequency/2-1 then --If not timeout yet, increase the counter
TIMEOUT_COUNTER <= TIMEOUT_COUNTER + 1;
else --Timeout. Proceed to send *T
CMD <= TIMEOUT;
TIMEOUT_COUNTER <= 0;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause |
bzero/freezing-spice | src/if_pkg.vhd | 2 | 493 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
package if_pkg is
-- inputs to Instruction Fetch stage
type if_in is record
insn : word;
load_pc : std_logic;
next_pc : word;
stall : std_logic;
end record if_in;
-- outputs from Instruction Fetch stage
type if_out is record
fetch_addr : word;
pc : word;
end record if_out;
end package if_pkg;
| bsd-3-clause |
bzero/freezing-spice | src/if.vhd | 2 | 2389 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.if_pkg.all;
entity instruction_fetch is
port (clk : in std_logic;
rst_n : in std_logic;
d : in if_in;
q : out if_out);
end entity instruction_fetch;
architecture Behavioral of instruction_fetch is
-------------------------------------------------
-- Types
-------------------------------------------------
type registers is record
pc : unsigned(word'range);
npc : unsigned(word'range);
end record registers;
-------------------------------------------------
-- Signals
-------------------------------------------------
signal r, rin : registers;
signal zero : std_logic := '1';
-------------------------------------------------
-- Constants
-------------------------------------------------
constant c_four : unsigned(2 downto 0) := to_unsigned(4, 3);
begin -- architecture Behavioral
-------------------------------------------------
-- assign outputs
-------------------------------------------------
q.fetch_addr <= std_logic_vector(rin.pc);
q.pc <= std_logic_vector(r.pc);
-------------------------------------------------
-- PC mux
-------------------------------------------------
pc_next_proc : process (d, r, zero) is
variable v : registers;
begin -- process pc_next_proc
-- defaults
v := r;
if (zero = '1') then
v.pc := (others => '0');
elsif (d.load_pc = '1') then
v.pc := unsigned(d.next_pc);
elsif (d.stall = '1') then
v.pc := r.pc;
else
v.pc := r.pc + c_four;
end if;
rin <= v;
end process pc_next_proc;
-------------------------------------------------
-- create the Program Counter register
-------------------------------------------------
pc_reg_proc : process (clk, rst_n) is
begin -- process pc_reg
if (rst_n = '0') then
r.pc <= (others => '0');
zero <= '1';
elsif (rising_edge(clk)) then
r <= rin;
zero <= '0';
end if;
end process pc_reg_proc;
end architecture Behavioral;
| bsd-3-clause |
iti-luebeck/RTeasy1 | src/main/resources/vhdltmpl/sram_control.vhd | 3 | 892 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sram_control IS
GENERIC(data_width : positive);
PORT(
CLK, RESET : IN std_logic;
C_WRITE, C_READ : IN std_logic;
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
TO_DATA_IN : OUT std_logic_vector(data_width-1 DOWNTO 0);
CS, WE : OUT std_logic;
SELECT_ALL : OUT std_logic
);
END sram_control;
ARCHITECTURE primitive OF sram_control IS
SIGNAL reset_on : std_logic;
BEGIN
reset_logic: PROCESS
BEGIN
reset_on <= '0';
WAIT UNTIL RESET='1';
WAIT UNTIL falling_edge(CLK);
reset_on <= '1';
WAIT UNTIL rising_edge(CLK);
END PROCESS;
SELECT_ALL <= reset_on;
WE <= (NOT CLK) AND (reset_on OR (NOT C_READ));
CS <= (NOT CLK) AND (C_WRITE OR C_READ);
TO_DATA_IN <= (OTHERS => '0') WHEN reset_on='1'
ELSE DATA_IN;
END primitive;
| bsd-3-clause |
iti-luebeck/RTeasy1 | src/main/resources/vhdltmpl/cu_entity.vhd | 3 | 248 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY %%COMPONENT_NAME_cu IS
PORT(
CLK, RESET : IN std_logic;
C : OUT std_logic_vector(0 TO %%C_MAX);
I : IN std_logic_vector(0 TO %%I_MAX)
);
END %%COMPONENT_NAME_cu; | bsd-3-clause |
iti-luebeck/RTeasy1 | src/main/resources/vhdltmpl/sram_array_comp.vhd | 1 | 417 | COMPONENT sram_array
GENERIC(addr_width, data_width : positive);
PORT(
CS, WE : IN std_logic;
SELECT_ALL : IN std_logic;
ADDR : IN std_logic_vector(addr_width-1 DOWNTO 0);
DATA_IN : IN std_logic_vector(data_width-1 DOWNTO 0);
DATA_OUT : OUT std_logic_vector(data_width-1 DOWNTO 0)
);
END COMPONENT;
FOR ALL : sram_array USE ENTITY WORK.sram_array(primitive);
| bsd-3-clause |
bzero/freezing-spice | src/compare_unit.vhd | 2 | 2313 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
use work.decode_pkg.all;
entity compare_unit is
port (
branch_type : in branch_type_t;
op1 : in word;
op2 : in word;
compare_result : out std_logic);
end entity compare_unit;
architecture behavioral of compare_unit is
signal compare : std_logic;
begin -- architecture behavioral
-- assign output
compare_result <= compare;
-- purpose: compares two numbers according to branch_type
-- type : combinational
-- inputs : branch_type, op1, op2
-- outputs: compare_result
compare_proc: process (branch_type, op1, op2) is
variable ou1, ou2 : unsigned(31 downto 0);
variable os1, os2 : signed(31 downto 0);
begin -- process compare_proc
ou1 := unsigned(op1);
os1 := signed(op1);
ou2 := unsigned(op2);
os2 := signed(op2);
compare <= '0';
case (branch_type) is
when BEQ =>
if op1 = op2 then
compare <= '1';
else
compare <= '0';
end if;
when BNE =>
if op1 /= op2 then
compare <= '1';
else
compare <= '0';
end if;
when BLT =>
if os1 < os2 then
compare <= '1';
else
compare <= '0';
end if;
when BGE =>
if os1 >= os2 then
compare <= '1';
else
compare <= '0';
end if;
when BLTU =>
if ou1 < ou2 then
compare <= '1';
else
compare <= '0';
end if;
when BGEU =>
if ou1 >= ou2 then
compare <= '1';
else
compare <= '0';
end if;
when others => compare <= '0';
end case;
end process compare_proc;
end architecture behavioral;
| bsd-3-clause |
eamadio/fpgaMSP430 | fmsp430/core/fmsp_register_file.vhd | 1 | 15186 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_register_file.vhd
--!
--! @brief fpgaMSP430 Register files
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_functions.all;
entity fmsp_register_file is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
alu_stat : in std_logic_vector(3 downto 0); --! ALU Status {V,N,Z,C}
alu_stat_wr : in std_logic_vector(3 downto 0); --! ALU Status write {V,N,Z,C}
inst_bw : in std_logic; --! Decoded Inst: byte width
inst_dest : in std_logic_vector(15 downto 0); --! Register destination selection
inst_src : in std_logic_vector(15 downto 0); --! Register source selection
pc : in std_logic_vector(15 downto 0); --! Program counter
reg_dest_val : in std_logic_vector(15 downto 0); --! Selected register destination value
reg_dest_wr : in std_logic; --! Write selected register destination
reg_pc_call : in std_logic; --! Trigger PC update for a CALL instruction
reg_sp_val : in std_logic_vector(15 downto 0); --! Stack Pointer next value
reg_sp_wr : in std_logic; --! Stack Pointer write
reg_sr_wr : in std_logic; --! Status register update for RETI instruction
reg_sr_clr : in std_logic; --! Status register clear for interrupts
reg_incr : in std_logic; --! Increment source register
--! OUTPUTs
cpuoff : out std_logic; --! Turns off the CPU
gie : out std_logic; --! General interrupt enable
oscoff : out std_logic; --! Turns off LFXT1 clock input
pc_sw : out std_logic_vector(15 downto 0); --! Program counter software value
pc_sw_wr : out std_logic; --! Program counter software write
reg_dest : out std_logic_vector(15 downto 0); --! Selected register destination content
reg_src : out std_logic_vector(15 downto 0); --! Selected register source content
scg0 : out std_logic; --! System clock generator 1. Turns off te DCO
scg1 : out std_logic; --! System clock generator 1. Turns off the SMmclk
status : out std_logic_vector(3 downto 0) --! R2 Status {V,N,Z,C}
);
end entity fmsp_register_file;
architecture RTL of fmsp_register_file is
--type single_register is std_logic_vector(15 downto 0);--
type array_16registers is array(0 to 15) of std_logic_vector(15 downto 0);
type fmsp_register_file_in_type is record
alu_stat : std_logic_vector(3 downto 0); --! ALU Status {V,N,Z,C}
alu_stat_wr : std_logic_vector(3 downto 0); --! ALU Status write {V,N,Z,C}
inst_bw : std_logic; --! Decoded Inst: byte width
inst_dest : std_logic_vector(15 downto 0); --! Register destination selection
inst_src : std_logic_vector(15 downto 0); --! Register source selection
pc : std_logic_vector(15 downto 0); --! Program counter
reg_dest_val : std_logic_vector(15 downto 0); --! Selected register destination value
reg_dest_wr : std_logic; --! Write selected register destination
reg_pc_call : std_logic; --! Trigger PC update for a CALL instruction
reg_sp_val : std_logic_vector(15 downto 0); --! Stack Pointer next value
reg_sp_wr : std_logic; --! Stack Pointer write
reg_sr_wr : std_logic; --! Status register update for RETI instruction
reg_sr_clr : std_logic; --! Status register clear for interrupts
reg_incr : std_logic; --! Increment source register
end record;
type reg_type is record
--! From outside of module
--! Internal mess of module
-- incr_op : std_logic_vector(15 downto 0);
-- reg_incr_val : std_logic_vector(15 downto 0);
-- reg_dest_val_in : std_logic_vector(15 downto 0);
-- inst_src_in : std_logic_vector(15 downto 0);
-- r1_wr : std_logic;
-- r1_inc : std_logic;
-- r2_wr : std_logic;
-- r2_c : std_logic; --! C
-- r2_z : std_logic; --! Z
-- r2_n : std_logic; --! N
-- r2_nxt : std_logic_vector(7 downto 3);
-- r2_v : std_logic; --! V
-- reg_wr : std_logic_vector(15 downto 0);
-- reg_inc : std_logic_vector(15 downto 0);
regs_array : array_16registers;
--! To outside of module
-- cpuoff : std_logic; --! Turns off the CPU
-- gie : std_logic; --! General interrupt enable
-- oscoff : std_logic; --! Turns off LFXT1 clock input
-- pc_sw : std_logic_vector(15 downto 0); --! Program counter software value
-- pc_sw_wr : std_logic; --! Program counter software write
-- reg_dest : std_logic_vector(15 downto 0); --! Selected register destination content
-- reg_src : std_logic_vector(15 downto 0); --! Selected register source content
-- scg1 : std_logic; --! System clock generator 1. Turns off the SMmclk
-- status : std_logic_vector(3 downto 0) --! R2 Status {V,N,Z,C}
end record;
signal d : fmsp_register_file_in_type;
signal r : reg_type := ( regs_array => (Others => (Others => '0'))
);
signal rin : reg_type;
begin
d.alu_stat <= alu_stat;
d.alu_stat_wr <= alu_stat_wr;
d.inst_bw <= inst_bw;
d.inst_dest <= inst_dest;
d.inst_src <= inst_src;
d.pc <= pc;
d.reg_dest_val <= reg_dest_val;
d.reg_dest_wr <= reg_dest_wr;
d.reg_pc_call <= reg_pc_call;
d.reg_sp_val <= reg_sp_val;
d.reg_sp_wr <= reg_sp_wr;
d.reg_sr_wr <= reg_sr_wr;
d.reg_sr_clr <= reg_sr_clr;
d.reg_incr <= reg_incr;
COMB : process (d, r)
variable v : reg_type;
variable v_incr_op : std_logic_vector(15 downto 0);
variable v_reg_incr_val : std_logic_vector(15 downto 0);
variable v_reg_dest_val_in : std_logic_vector(15 downto 0);
variable v_inst_src_in : std_logic_vector(15 downto 0);
-- variable v_r0 : std_logic_vector(15 downto 0);
variable v_r1_wr : std_logic;
variable v_r1_inc : std_logic;
variable v_r2_wr : std_logic;
variable v_r2_c : std_logic; --! C
variable v_r2_z : std_logic; --! Z
variable v_r2_n : std_logic; --! N
variable v_r2_nxt : std_logic_vector(7 downto 3);
variable v_r2_v : std_logic; --! V
variable v_reg_wr : std_logic_vector(15 downto 0);
variable v_reg_inc : std_logic_vector(15 downto 0);
variable v_pc_sw : std_logic_vector(15 downto 0); --! Program counter software value
variable v_pc_sw_wr : std_logic; --! Program counter software write
variable v_reg_dest : std_logic_vector(15 downto 0); --! Selected register destination content
variable v_reg_src : std_logic_vector(15 downto 0); --! Selected register source content
variable UNUSED_reg_sp_val_0 : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
--! Source input selection mask (for interrupt support)
-------------------------------------------------------
if (d.reg_sr_clr = '1') then
v_inst_src_in := x"0004";
else
v_inst_src_in := d.inst_src;
end if;
REG_MUXING_SRC : for i in 0 to 15 loop
v_reg_src(i) := (d.pc(i) and v_inst_src_in(0))
or (r.regs_array(1)(i) and v_inst_src_in(1))
or (r.regs_array(2)(i) and v_inst_src_in(2))
or (r.regs_array(3)(i) and v_inst_src_in(3))
or (r.regs_array(4)(i) and v_inst_src_in(4))
or (r.regs_array(5)(i) and v_inst_src_in(5))
or (r.regs_array(6)(i) and v_inst_src_in(6))
or (r.regs_array(7)(i) and v_inst_src_in(7))
or (r.regs_array(8)(i) and v_inst_src_in(8))
or (r.regs_array(9)(i) and v_inst_src_in(9))
or (r.regs_array(10)(i) and v_inst_src_in(10))
or (r.regs_array(11)(i) and v_inst_src_in(11))
or (r.regs_array(12)(i) and v_inst_src_in(12))
or (r.regs_array(13)(i) and v_inst_src_in(13))
or (r.regs_array(14)(i) and v_inst_src_in(14))
or (r.regs_array(15)(i) and v_inst_src_in(15));
end loop;
--=============================================================================
--! 1) AUTOINCREMENT UNIT
--=============================================================================
if (d.inst_bw = '1') then
v_incr_op := x"0001";
else
v_incr_op := x"0002";
end if;
v_reg_incr_val := STD_LOGIC_VECTOR(UNSIGNED(v_reg_src) + UNSIGNED(v_incr_op));
if (d.inst_bw = '1') then
v_reg_dest_val_in := x"00" & d.reg_dest_val(7 downto 0);
else
v_reg_dest_val_in := d.reg_dest_val;
end if;
--=============================================================================
--! 2) SPECIAL REGISTERS (R1/R2/R3)
--=============================================================================
--! R0: Program counter
-----------------------
--v.regs_array(0) := d.pc;
--v_r0 := d.pc;
v_pc_sw := v_reg_dest_val_in;
v_pc_sw_wr := (d.inst_dest(0) and d.reg_dest_wr) or d.reg_pc_call;
--! R1: Stack pointer
---------------------
v_r1_wr := d.inst_dest(1) and d.reg_dest_wr;
v_r1_inc := v_inst_src_in(1) and d.reg_incr;
if (v_r1_wr = '1') then
v.regs_array(1) := v_reg_dest_val_in and x"FFFE";
elsif (d.reg_sp_wr = '1') then
v.regs_array(1) := d.reg_sp_val and x"FFFE";
elsif (v_r1_inc = '1') then
v.regs_array(1) := v_reg_incr_val and x"FFFE";
end if;
UNUSED_reg_sp_val_0 := d.reg_sp_val(0);
--! R2: Status register
-----------------------
v_r2_wr := (d.inst_dest(2) and d.reg_dest_wr) or d.reg_sr_wr;
--! C
if (d.alu_stat_wr(0) = '1') then
v_r2_c := d.alu_stat(0);
else
if (v_r2_wr = '1') then
v_r2_c := v_reg_dest_val_in(0);
else
v_r2_c := r.regs_array(2)(0);
end if;
end if;
--! Z
if (d.alu_stat_wr(1) = '1') then
v_r2_z := d.alu_stat(1);
else
if (v_r2_wr = '1') then
v_r2_z := v_reg_dest_val_in(1);
else
v_r2_z := r.regs_array(2)(1);
end if;
end if;
--! N
if (d.alu_stat_wr(2) = '1') then
v_r2_n := d.alu_stat(2);
else
if (v_r2_wr = '1') then
v_r2_n := v_reg_dest_val_in(2);
else
v_r2_n := r.regs_array(2)(2);
end if;
end if;
--! NXT
if (v_r2_wr = '1') then
v_r2_nxt := v_reg_dest_val_in(7 downto 3);
else
v_r2_nxt := r.regs_array(2)(7 downto 3);
end if;
--! V
if (d.alu_stat_wr(3) = '1') then
v_r2_v := d.alu_stat(3);
else
if (v_r2_wr = '1') then
v_r2_v := v_reg_dest_val_in(8);
else
v_r2_v := r.regs_array(2)(8);
end if;
end if;
--R2_REG : process(mclk,mrst)
if (d.reg_sr_clr = '1') then
v.regs_array(2) := v_reg_dest_val_in;
else
v.regs_array(2) := "0000000" & v_r2_v & v_r2_nxt & v_r2_n & v_r2_z & v_r2_c;
end if;
--! R3: Constant generator
--------------------------
v_reg_wr(3) := d.inst_dest(3) and d.reg_dest_wr;
v_reg_inc(3) := v_inst_src_in(3) and d.reg_incr;
--R3_REG : process(mclk,mrst)
if (v_reg_wr(3) = '1') then
v.regs_array(3) := v_reg_dest_val_in;
elsif (v_reg_inc(3) = '1') then
v.regs_array(3) := v_reg_incr_val;
end if;
--=============================================================================
--! 4) GENERAL PURPOSE REGISTERS (R4...R15)
--=============================================================================
-- GENERAL_PURPOSE_REGISTERS : process(mclk,mrst)
for i in 4 to 15 loop
if ( (d.inst_dest(i) and d.reg_dest_wr) = '1') then
v.regs_array(i) := v_reg_dest_val_in;
elsif ( (v_inst_src_in(i) and d.reg_incr) = '1') then
v.regs_array(i) := v_reg_incr_val;
end if;
end loop;
--=============================================================================
--! 5) READ MUX
--=============================================================================
REG_MUXING_DEST : for i in 0 to 15 loop
v_reg_dest(i) := (d.pc(i) and d.inst_dest(0))
or (r.regs_array(1)(i) and d.inst_dest(1))
or (r.regs_array(2)(i) and d.inst_dest(2))
or (r.regs_array(3)(i) and d.inst_dest(3))
or (r.regs_array(4)(i) and d.inst_dest(4))
or (r.regs_array(5)(i) and d.inst_dest(5))
or (r.regs_array(6)(i) and d.inst_dest(6))
or (r.regs_array(7)(i) and d.inst_dest(7))
or (r.regs_array(8)(i) and d.inst_dest(8))
or (r.regs_array(9)(i) and d.inst_dest(9))
or (r.regs_array(10)(i) and d.inst_dest(10))
or (r.regs_array(11)(i) and d.inst_dest(11))
or (r.regs_array(12)(i) and d.inst_dest(12))
or (r.regs_array(13)(i) and d.inst_dest(13))
or (r.regs_array(14)(i) and d.inst_dest(14))
or (r.regs_array(15)(i) and d.inst_dest(15));
end loop;
--! drive register inputs
rin <= v;
--! drive module outputs
status <= r.regs_array(2)(8) & r.regs_array(2)(2 downto 0);
scg1 <= r.regs_array(2)(7);
scg0 <= r.regs_array(2)(6);
oscoff <= r.regs_array(2)(5);
cpuoff <= r.regs_array(2)(4) or (v_r2_nxt(4) and v_r2_wr);
gie <= r.regs_array(2)(3);
pc_sw <= v_pc_sw;
pc_sw_wr <= v_pc_sw_wr;
reg_dest <= v_reg_dest;
reg_src <= v_reg_src;
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r.regs_array <= (Others => (Others => '0'));
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
end RTL; | bsd-3-clause |
loa-org/loa-hdl | modules/peripheral_register/hdl/reg_file_pkg.vhd | 1 | 5846 | -------------------------------------------------------------------------------
-- Title : Components package (generated by Emacs VHDL Mode 3.33.6)
-- Project :
-------------------------------------------------------------------------------
-- File : components.vhd
-- Author : Calle <calle@Alukiste>
-- Created : 2012-03-11
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
package reg_file_pkg is
type reg_file_type is array (natural range <>) of std_logic_vector(15 downto 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- A single 16-bit register.
component peripheral_register is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#;
RESET_IMPL : reset_type := none);
port (
dout_p : out std_logic_vector(15 downto 0);
din_p : in std_logic_vector(15 downto 0);
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reset : in std_logic;
clk : in std_logic);
end component peripheral_register;
-- Several (2**(REG_ADDR_BIT)) 16-bit registers.
component reg_file
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
REG_ADDR_BIT : natural;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
reg_o : out reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reg_i : in reg_file_type(2**REG_ADDR_BIT-1 downto 0);
reset : in std_logic;
clk : in std_logic);
end component;
component reg_file_bram is
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
bram_data_i : in std_logic_vector(15 downto 0);
bram_data_o : out std_logic_vector(15 downto 0);
bram_addr_i : in std_logic_vector(9 downto 0);
bram_we_p : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component reg_file_bram;
component reg_file_bram_double_buffered
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
bram_data_i : in std_logic_vector(35 downto 0);
bram_data_o : out std_logic_vector(35 downto 0);
bram_addr_i : in std_logic_vector(7 downto 0);
bram_we_p : in std_logic;
irq_o : out std_logic;
ack_i : in std_logic;
ready_i : in std_logic;
enable_o : out std_logic;
bank_x_o : out std_logic;
bank_y_o : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component double_buffering is
port (
ready_p : in std_logic;
enable_p : out std_logic;
irq_p : out std_logic;
ack_p : in std_logic;
bank_p : out std_logic;
clk : in std_logic);
end component double_buffering;
procedure readWord(
constant addr : natural range 0 to 2**15-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic);
procedure writeWord (
constant addr : in natural range 0 to 2**15-1;
constant data : in natural range 0 to 2**16-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic);
end reg_file_pkg;
-------------------------------------------------------------------------------
package body reg_file_pkg is
----------------------------------------------------------------------------
-- Debug functions to simulate bus activity
----------------------------------------------------------------------------
-- Read a word from the internal bus
-- Example usage: readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
procedure readWord(
constant addr : natural range 0 to 2**15-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic
) is
begin -- procedure readWord
if (clk = '1') then
wait until falling_edge(clk);
end if;
bus_i.addr <= std_logic_vector(to_unsigned(addr, bus_i.addr'length));
bus_i.data <= x"1234"; -- dummy data in read cycle
bus_i.re <= '1';
wait until rising_edge(clk);
-- ret := bus_o.data;
wait until falling_edge(clk);
bus_i.re <= '0';
end procedure readWord;
-- Write a word to the internal bus
-- Example usage: writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
procedure writeWord (
constant addr : in natural range 0 to 2**15-1;
constant data : in natural range 0 to 2**16-1;
signal bus_i : out busdevice_in_type;
signal clk : in std_logic) is
begin -- procedure writeWord
if (clk = '1') then
wait until falling_edge(clk);
end if;
bus_i.addr <= std_logic_vector(to_unsigned(addr, bus_i.addr'length));
bus_i.data <= std_logic_vector(to_unsigned(data, bus_i.data'length));
bus_i.we <= '1';
wait until rising_edge(clk);
wait until falling_edge(clk);
bus_i.we <= '0';
end procedure writeWord;
end package body reg_file_pkg;
| bsd-3-clause |
loa-org/loa-hdl | modules/imotor/tb/imotor_module_tb.vhd | 2 | 4406 | -------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_module"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_module_tb is
end entity imotor_module_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#0100#;
constant MOTORS : positive := 2;
-- Component ports
signal tx_out : std_logic_vector(MOTORS-1 downto 0);
signal rx_in : std_logic_vector(MOTORS-1 downto 0) := (others => '1');
signal rx_in_can : std_logic_vector(MOTORS-1 downto 0); -- simulated signal on the CAN link
signal tx_busy_s : std_logic;
signal tx_data_s : std_logic_vector(7 downto 0) := (others => '0');
signal tx_empty_s : std_logic := '1';
signal tx_re_s : std_logic;
signal clk_tx_s : std_logic := '0';
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
-- clock
signal clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
-- MUT
imotor_module_1 : entity work.imotor_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
DATA_WORDS_READ => 3,
DATA_WORDS_SEND => 2,
MOTORS => MOTORS)
port map (
tx_out_p => tx_out,
rx_in_p => rx_in_can,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- Simulates the answer of an iMotor
uart_tx_1 : entity work.uart_tx
port map (
txd_p => rx_in(0),
busy_p => tx_busy_s,
data_p => tx_data_s,
empty_p => tx_empty_s,
re_p => tx_re_s,
clk_tx_en => clk_tx_s,
clk => clk);
-- clock generation 50 MHz
clk <= not clk after 10 ns;
-- Generate a Tx bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_s <= '1';
wait until rising_edge(clk);
clk_tx_s <= '0';
wait for 970 ns;
end process bitclock;
-- CAN simulation
can_sim : for ii in 0 to MOTORS-1 generate
rx_in_can(ii) <= '0' when rx_in(ii) = '0' or tx_out(ii) = '0' else '1';
end generate can_sim;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '1';
-- Fill registers at simulation start
-- iMotor #0, PWM
writeWord(addr => 16#0100#, data => 16#2211#, bus_i => bus_i, clk => clk);
-- iMotor #0, CUR
writeWord(addr => 16#0101#, data => 16#4433#, bus_i => bus_i, clk => clk);
-- iMotor #1, PWM
writeWord(addr => 16#0102#, data => 16#6655#, bus_i => bus_i, clk => clk);
-- iMotor #1, CUR
writeWord(addr => 16#0103#, data => 16#8877#, bus_i => bus_i, clk => clk);
wait for 300 us;
tx_data_s <= x"51";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"aa";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"bb";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"cc";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"dd";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
tx_data_s <= x"a1";
tx_empty_s <= '0';
wait until falling_edge(tx_re_s);
tx_empty_s <= '1';
wait;
end process WaveGen_Proc;
end architecture behavourial;
| bsd-3-clause |
loa-org/loa-hdl | modules/fifo_sync/tb/fifo_sync_tb.vhd | 2 | 2816 | -------------------------------------------------------------------------------
-- Title : Synchronous FIFO Testbench
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A very plain FIFO, synchronous interfaces.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fifo_sync_pkg.all;
-------------------------------------------------------------------------------
entity fifo_sync_tb is
end entity fifo_sync_tb;
-------------------------------------------------------------------------------
architecture tb of fifo_sync_tb is
use work.fifo_sync_pkg.all;
-- component ports
constant data_width : natural := 8;
constant address_width : natural := 4;
signal di : std_logic_vector(data_width -1 downto 0);
signal wr : std_logic := '0';
signal full : std_logic;
signal do : std_logic_vector(data_width -1 downto 0);
signal rd : std_logic := '0';
signal empty : std_logic;
signal r : std_logic := '0';
signal w : std_logic := '0';
-- clock
signal Clk : std_logic := '1';
begin -- architecture behavourial
-- component instantiation
DUT : fifo_sync
generic map (
data_width => data_width,
address_width => address_width)
port map (
di => di,
wr => wr,
full => full,
do => do,
rd => rd,
empty => empty,
valid => open,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
process
variable n : integer := 0;
begin
wait until Clk = '1';
if w = '1' and full = '0' then
wr <= '1';
di <= std_logic_vector(to_unsigned(n, 8));
n := n+1;
else
wr <= '0';
end if;
end process;
process
variable n : integer := 0;
begin
wait until Clk = '1';
if empty = '0' and r = '1' then
rd <= '1';
else
rd <= '0';
end if;
end process;
process
begin
w <= '1';
wait for 300 ns;
w <= '0';
wait for 100 ns;
r <= '1';
wait for 50 ns;
r <= '0';
wait for 100 ns;
end process;
end architecture tb;
configuration fifo_sync_tb_cfg of fifo_sync_tb is
for tb
end for;
end fifo_sync_tb_cfg;
| bsd-3-clause |
loa-org/loa-hdl | modules/dds/tb/dds_module_tb.vhd | 1 | 4280 | -------------------------------------------------------------------------------
-- Title : Testbench for design "dds_module"
-------------------------------------------------------------------------------
-- Author : Carl Treudler
-- Standard :
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dds_module_pkg.all;
use work.bus_pkg.all;
use work.reset_pkg.all;
-------------------------------------------------------------------------------
entity dds_module_tb is
end dds_module_tb;
-------------------------------------------------------------------------------
architecture tb of dds_module_tb is
-- component generics
constant BASE_ADDRESS : positive := 16#400#;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type :=
(addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal dout : std_logic_vector(15 downto 0);
signal reset : std_logic;
signal clk : std_logic := '1';
begin
dds_module_1 : entity work.dds_module
generic map (
BASE_ADDRESS => BASE_ADDRESS,
RESET_IMPL => none)
port map (
bus_o => bus_o,
bus_i => bus_i,
dout => dout,
reset => reset,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- reset generation
reset <= '1', '0' after 50 ns;
waveform : process
begin
wait until falling_edge(reset);
wait for 20 us;
---------------------------------------------------------------------------
-- load some data into waveform ram
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#400#, 15));
bus_i.data <= x"0123";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#401#, 15));
bus_i.data <= x"0124";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#402#, 15));
bus_i.data <= x"0125";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 1 us;
---------------------------------------------------------------------------
-- Set Phase increment
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#801#, 15));
bus_i.data <= x"0001";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#802#, 15));
bus_i.data <= x"0020";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
---------------------------------------------------------------------------
-- Set Phase -- 0°
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#803#, 15));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#804#, 15));
bus_i.data <= x"0000";
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
---------------------------------------------------------------------------
-- set Control Register
---------------------------------------------------------------------------
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#800#, 15));
bus_i.data <= x"0002"; -- load accu0
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait until rising_edge(clk);
bus_i.addr <= std_logic_vector(to_unsigned(16#800#, 15));
bus_i.data <= x"0001"; -- enable nco0
bus_i.we <= '1';
wait until rising_edge(clk);
bus_i.we <= '0';
wait for 30 us;
end process waveform;
end tb;
| bsd-3-clause |
loa-org/loa-hdl | modules/uss_tx/hdl/serialiser.vhd | 2 | 3016 | -------------------------------------------------------------------------------
-- Title : Modulator
-------------------------------------------------------------------------------
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity serialiser is
generic (
BITPATTERN_WIDTH : positive := 32
);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic
);
end serialiser;
-------------------------------------------------------------------------------
architecture behavioural of serialiser is
type serialiser_type is record
counter : integer range 0 to BITPATTERN_WIDTH;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : serialiser_type := (counter => 0);
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
bitstream_out_p <= pattern_in_p(r.counter);
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(clk_bit, r)
variable v : serialiser_type;
begin
v := r;
if clk_bit = '1' then
v.counter := v.counter + 1;
if v.counter = BITPATTERN_WIDTH then
v.counter := 0;
end if;
end if;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
| bsd-3-clause |
loa-org/loa-hdl | modules/dds/hdl/dds_module_pkg.vhd | 1 | 1255 | -------------------------------------------------------------------------------
-- Title : Direct digital synhtesis module
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2015-08-24
-------------------------------------------------------------------------------
-- Copyright (c) 2015, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library work;
use work.bus_pkg.all;
use work.reset_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
package dds_module_pkg is
component dds_module is
generic (
BASE_ADDRESS : integer range 0 to 2**15-1;
RESET_IMPL : reset_type := none);
port (
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
dout : out std_logic_vector(15 downto 0);
reset : in std_logic;
clk : in std_logic);
end component dds_module;
end package dds_module_pkg;
| bsd-3-clause |
loa-org/loa-hdl | modules/spislave/tb/spi_slave_tb.vhd | 2 | 3411 | -------------------------------------------------------------------------------
-- Title : Testbench for design "spi_slave"
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.spislave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spi_slave_tb is
end spi_slave_tb;
-------------------------------------------------------------------------------
architecture tb of spi_slave_tb is
-- component ports
signal mosi : std_logic;
signal miso : std_logic;
signal sck : std_logic;
signal csn : std_logic;
signal clk : std_logic := '1';
signal bus_o : busmaster_out_type;
signal bus_i : busmaster_in_type;
signal bus_data : unsigned(15 downto 0) := (others => '0');
signal debug_addr : std_logic_vector(14 downto 0);
signal debug_data : std_logic_vector(15 downto 0);
begin -- tb
DUT : spi_slave port map (
--ireg => open,
--bit_cnt => open,
miso_p => miso,
mosi_p => mosi,
sck_p => sck,
csn_p => csn,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
Clk <= not Clk after 5.0 ns;
-- Change the bus data to find out when exactly the bus is sampled
process (clk) is
begin -- process
if rising_edge(clk) then -- rising clock edge
bus_i.data <= std_logic_vector(bus_data);
bus_data <= bus_data + 1;
end if;
end process;
process
variable d : std_logic_vector(31 downto 0);
begin
debug_addr <= std_logic_vector(to_unsigned(16#0ff#, 15));
debug_data <= x"fe35";
-- read access to addr 0x7000 with 0x0000 as dummy data.
spiReadWord(addr => 16#7000#, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
-- write access to addr 0x00ff with data 0xfe35
spiWriteWord(addr => debug_addr, data => debug_data, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
--
wait for 1 us;
d := X"8209" & X"cd43";
-- start
csn <= '1';
sck <= '0';
mosi <= '0';
wait for 250 ns;
csn <= '0';
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
-- no pause between two transfers:
if false then
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
wait for 250 ns;
csn <= '0';
wait for 250 ns;
end if;
-- write access to addr 0xf0f with data 0x1234
d := X"8f0f" & X"1234";
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
end process;
end tb;
| bsd-3-clause |
loa-org/loa-hdl | modules/peripheral_register/tb/reg_file_tb.vhd | 2 | 3324 | -------------------------------------------------------------------------------
-- Title : Testbench for design "reg_file"
-------------------------------------------------------------------------------
-- Author : Calle <calle@Alukiste>
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.bus_pkg.all;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity reg_file_tb is
end reg_file_tb;
-------------------------------------------------------------------------------
architecture tb of reg_file_tb is
-- component generics
constant BASE_ADDRESS : integer range 0 to 16#7FFF# := 16#0010#;
constant REG_ADDR_BIT : natural := 1;
-- component ports
signal bus_o : busdevice_out_type;
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal reg_o : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
signal reg_i : reg_file_type(2**REG_ADDR_BIT-1 downto 0);
-- clock
signal clk : std_logic := '1';
type comment_type is (idle, write, read);
signal comment : comment_type := idle;
begin -- tb
-- component instantiation
DUT : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- Reset
reg_i <= (others => (others => '0'));
reg_i(0)(3 downto 0) <= "0001";
reg_i(1)(3 downto 0) <= "0010";
bus_i.addr <= (others => '0');
bus_i.data <= (others => '0');
bus_i.re <= '0';
bus_i.we <= '0';
wait until Clk = '1';
comment <= write;
writeWord(addr => 16#0010#, data => 16#0055#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
writeWord(addr => 16#0011#, data => 16#005f#, bus_i => bus_i, clk => clk);
wait until Clk = '1';
wait until Clk = '1';
-- read the registers
-- expected data is the input to the register_file reg_i(0) and reg_i(1)
comment <= read;
readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk);
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
-- do the same reads, but the DUT shouldn't react
-- bus data should be 0000
readWord(addr => BASE_ADDRESS + 2, bus_i => bus_i, clk => clk);
-- read from correct address again
readWord(addr => BASE_ADDRESS + 1, bus_i => bus_i, clk => clk);
wait for 1000 ns;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
| bsd-3-clause |
loa-org/loa-hdl | modules/onewire/hdl/onewire_pkg.vhd | 1 | 1627 | -------------------------------------------------------------------------------
-- Title : Onewire Master Configuration Package
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package onewire_pkg is
type onewire_out_type is record
d : std_logic_vector(7 downto 0);
busy : std_logic;
err : std_logic;
end record;
type onewire_in_type is record
d : std_logic_vector(7 downto 0);
re : std_logic;
we : std_logic;
reset_bus : std_logic;
end record;
type onewire_bus_out_type is record
d : std_logic;
en_driver : std_logic;
end record;
type onewire_bus_in_type is record
d : std_logic;
end record;
component onewire
port (
onewire_in : in onewire_in_type;
onewire_out : out onewire_out_type;
onewire_bus_in : in onewire_bus_in_type;
onewire_bus_out : out onewire_bus_out_type;
clk : in std_logic);
end component;
end onewire_pkg;
| bsd-3-clause |
loa-org/loa-hdl | modules/utils/hdl/utils_pkg.vhd | 1 | 5036 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package utils_pkg is
-- Calculates the number of bits required to encode the given number
--
-- Note that this function is not intended to synthesize directly into
-- hardware, rather it is used to generate constants for synthesized
-- hardware.
--
-- Example:
-- entity foo is
-- generic(
-- ABC : positive);
-- port(
-- xzy : out std_logic_vector(required_bits(ABC) downto 0));
-- end foo;
function required_bits (value : natural) return natural;
-- Another function which does the same, up to 32 bits
function log2 (val : integer) return natural;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer;
function minn(L : integer;
R : integer)
return integer;
----------------------------------------------------------------------------
-- replacement for std_logic_arith
-- works with unsigneds
-- see http://www.lothar-miller.de/s9y/archives/14-Numeric_Std.html
function conv_integer(
vec : std_logic_vector)
return integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector;
----------------------------------------------------------------------------
component clock_divider is
generic (
DIV : positive);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component;
-- Requires MUL <= DIV
component fractional_clock_divider is
generic (
DIV : positive;
MUL : positive;
WIDTH : positive := 16);
port (
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider;
-- Requires mul <= div
component fractional_clock_divider_variable is
generic (
WIDTH : positive);
port (
div : in std_logic_vector(WIDTH-1 downto 0);
mul : in std_logic_vector(WIDTH-1 downto 0);
clk_out_p : out std_logic;
clk : in std_logic);
end component fractional_clock_divider_variable;
----------------------------------------------------------------------------
component event_hold_stage is
port (
dout_p : out std_logic;
din_p : in std_logic;
period_p : in std_logic;
clk : in std_logic);
end component event_hold_stage;
component edge_detect is
port (
async_sig : in std_logic;
clk : in std_logic;
rise : out std_logic;
fall : out std_logic);
end component edge_detect;
----------------------------------------------------------------------------
component dff is
port (
dout_p : out std_logic;
din_p : in std_logic;
set_p : in std_logic;
reset_p : in std_logic;
ce_p : in std_logic;
clk : in std_logic);
end component dff;
end package utils_pkg;
package body utils_pkg is
function required_bits (value : natural) return natural is
begin
if value <= 0 then
return 0;
elsif value = 1 then
return 1;
elsif value < 8 then
return integer(ceil(log2(real(value))));
else
-- FIXME: Why is this hack necessary?
-- Otherwise the values for 2**x (x >= 3) are calculated wrong.
-- E.g.:
-- required_bits(8) = 3 != 4
-- required_bits(16) = 4 != 5
-- see ../tb/utils_tb.vhd
return integer(ceil(log2(real(value) + 0.5)));
end if;
end function;
function log2 (val : integer) return natural is
variable res : positive;
begin -- log2
for i in 1 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop; -- i
return res;
end log2;
----------------------------------------------------------------------------
function max(L : integer;
R : integer)
return integer is
begin -- max
if L > R then
return L;
else
return R;
end if;
end max;
function minn(L : integer;
R : integer)
return integer is
begin -- min
if L < R then
return L;
else
return R;
end if;
end minn;
----------------------------------------------------------------------------
function conv_integer(
vec : std_logic_vector)
return integer is
begin
return to_integer(unsigned(vec));
end conv_integer;
function conv_std_logic_vector (
int : natural;
len : natural)
return std_logic_vector is
begin -- conv_std_logic_vector
return std_logic_vector(to_unsigned(int, len));
end conv_std_logic_vector;
end package body utils_pkg;
| bsd-3-clause |
loa-org/loa-hdl | modules/ir_rx/tb/ir_rx_module_timestamp_tb.vhd | 2 | 3560 | -------------------------------------------------------------------------------
-- Title : Testbench for design "ir_rx_module" with timestamps
------------------------------------------------------------------------------
-- File : ir_rx_module_timestamp_tb.vhd
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.adc_ltc2351_pkg.all;
use work.ir_rx_module_pkg.all;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity ir_rx_module_timestamp_tb is
end ir_rx_module_timestamp_tb;
-------------------------------------------------------------------------------
architecture tb of ir_rx_module_timestamp_tb is
-- component generics
constant BASE_ADDRESS_RESULTS : integer := 16#0800#;
constant BASE_ADDRESS_COEFS : integer := 16#0010#;
constant BASE_ADDRESS_TIMESTAMP : integer := 16#0100#;
constant TIMESTAMP_WIDTH : natural := 48;
-- component ports
signal adc_out_p : ir_rx_module_spi_out_type;
signal adc_in_p : ir_rx_module_spi_in_type := (others => (others => '0'));
signal sync_p : std_logic := '0';
signal bus_o : busdevice_out_type := (data => (others => '0'));
signal bus_i : busdevice_in_type := (addr => (others => '0'),
data => (others => '0'),
we => '0',
re => '0');
signal done_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal clk_sample_en : std_logic := '0';
-- timestamp
signal timestamp_s : timestamp_type;
-- clock
signal clk : std_logic := '1';
begin -- tb
ir_rx_module_1 : entity work.ir_rx_module
generic map (
BASE_ADDRESS_COEFS => BASE_ADDRESS_COEFS,
BASE_ADDRESS_RESULTS => BASE_ADDRESS_RESULTS,
BASE_ADDRESS_TIMESTAMP => BASE_ADDRESS_TIMESTAMP,
SAMPLES => 10)
port map (
adc_o_p => adc_out_p,
adc_i_p => adc_in_p,
adc_values_o_p => open,
sync_o_p => sync_p,
bus_o_p => bus_o,
bus_i_p => bus_i,
done_o_p => done_p,
ack_i_p => ack_p,
clk_sample_en_i_p => clk_sample_en,
timestamp_i_p => timestamp_s,
clk => clk);
timestamp_1 : entity work.timestamp_generator
port map (
timestamp_o_p => timestamp_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Trigger ADC conversions
WaveGen_Proc : process
begin
wait until clk = '1';
if done_p = '0' then
clk_sample_en <= '1';
end if;
wait until clk = '1';
clk_sample_en <= '0';
wait
for 7 us;
end process WaveGen_Proc;
-- Acknowledge if the module is finished
ack_proc : process
begin -- process ack_proc
wait until done_p = '1';
wait
for 5 us;
ack_p <= '1';
wait
for 1 us;
ack_p <= '0';
end process ack_proc;
end tb;
| bsd-3-clause |
loa-org/loa-hdl | modules/signalprocessing/tb/io_test.vhd | 2 | 1619 | -------------------------------------------------------------------------------
-- Title : Testbench for integer-to-real conversion
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Learning VHDL io.
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity io_test is
end entity io_test;
architecture tb of io_test is
signal clk : std_logic := '0';
signal s0 : std_logic_vector(15 downto 0) := (others => '0');
signal s1 : signed(15 downto 0) := (others => '0');
signal s2 : integer := 0;
signal s3 : real := 0.0;
type IntegerFileType is file of integer;
begin -- architecture tb
-- clock gen
clk <= not clk after 1 ms;
process (clk) is
variable cnt : integer := 0;
file data_out : IntegerFileType open write_mode is "my_file.bin";
variable fstatus : file_open_status;
begin -- process
if rising_edge(clk) then -- rising clock edge
s0 <= std_logic_vector(to_unsigned(cnt, 16));
write(data_out, s2);
cnt := cnt + 1;
end if;
end process;
s1 <= signed(s0);
s2 <= to_integer(s1);
s3 <= real(s2);
end architecture tb;
| bsd-3-clause |
loa-org/loa-hdl | modules/utils/tb/event_hold_stage_tb.vhd | 2 | 1172 |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity event_hold_stage_tb is
end event_hold_stage_tb;
architecture tb of event_hold_stage_tb is
signal dout : std_logic := '0';
signal din : std_logic := '0';
signal period : std_logic := '0';
signal clk : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : event_hold_stage
port map (
dout_p => dout,
din_p => din,
period_p => period,
clk => clk);
process
begin
wait for 10 NS;
din <= '1';
wait for 20 NS;
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
din <= '1';
wait for 20 NS;
period <= '0';
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 US;
end process;
end tb;
| bsd-3-clause |
loa-org/loa-hdl | modules/signalprocessing/tb/goertzel_control_unit_tb.vhd | 2 | 2850 | -------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_control_unit"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_control_unit_tb is
end entity goertzel_control_unit_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_control_unit_tb is
-- component generics
constant SAMPLES : positive := 5;
constant FREQUENCIES : positive := 2;
constant CHANNELS : positive := 3;
-- component ports
signal start_p : std_logic := '0';
signal ready_p : std_logic := '0';
signal bram_addr : std_logic_vector(7 downto 0) := (others => '0');
signal bram_we : std_logic := '0';
signal mux_delay1 : std_logic := '0';
signal mux_delay2 : std_logic := '0';
signal mux_coef : natural range FREQUENCIES-1 downto 0;
signal mux_input : natural range CHANNELS-1 downto 0;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_control_unit
generic map (
SAMPLES => SAMPLES,
FREQUENCIES => FREQUENCIES,
CHANNELS => CHANNELS)
port map (
start_p => start_p,
ready_p => ready_p,
bram_addr_p => bram_addr,
bram_we_p => bram_we,
mux_delay1_p => mux_delay1,
mux_delay2_p => mux_delay2,
mux_coef_p => mux_coef,
mux_input_p => mux_input,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
-- some delay
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
-- New 12 new samples from ADCs received: start control unit!
start_p <= '1';
wait until clk = '0';
start_p <= '0';
-- wait until all samples for all frequencies are processed and the
-- address counter was reset to 0
wait until bram_addr = "00000000";
-- restart
end process WaveGen_Proc;
end architecture tb;
| bsd-3-clause |
WigWagCo/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
mkreider/cocotb2 | examples/wb/hdl/cocotb_wb_loopback.vhd | 1 | 2571 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
entity cocotb_wb_loopback is
port (
clk: in std_logic;
reset_n : in std_logic;
clk2 : in std_logic;
reset_n2 : in std_logic;
wbm_cyc : in std_logic;
wbm_stb : in std_logic;
wbm_we : in std_logic;
wbm_sel : in std_logic_vector(3 downto 0);
wbm_adr : in std_logic_vector(31 downto 0);
wbm_datrd : out std_logic_vector(31 downto 0);
wbm_datwr : in std_logic_vector(31 downto 0);
wbm_stall: out std_logic;
wbm_ack: out std_logic;
wbm_err: out std_logic;
wbmo_cyc : out std_logic;
wbmo_stb : out std_logic;
wbmo_we : out std_logic;
wbmo_sel : out std_logic_vector(3 downto 0);
wbmo_adr : out std_logic_vector(31 downto 0);
wbmo_datrd : in std_logic_vector(31 downto 0);
wbmo_datwr : out std_logic_vector(31 downto 0);
wbmo_err: in std_logic;
wbmo_stall: in std_logic;
wbmo_ack: in std_logic
);
end entity;
architecture rtl of cocotb_wb_loopback is
signal s_master_in : t_wishbone_master_in;
signal s_master_out : t_wishbone_master_out;
signal reg : std_logic_vector(31 downto 0);
begin
s_master_out.we <= wbm_we;
s_master_out.stb <= wbm_stb;
s_master_out.dat <= wbm_datwr;
s_master_out.adr <= wbm_adr;
s_master_out.sel <= x"f";
s_master_out.cyc <= wbm_cyc;
-- s_master_in.dat <= reg;
wbm_datrd <= s_master_in.dat;
wbm_ack <= s_master_in.ack;
wbm_stall <= s_master_in.stall;
wbm_err <= s_master_in.err;
wbmo_we <= s_master_out.we;
wbmo_stb <= s_master_out.stb;
wbmo_datwr <= s_master_out.dat;
wbmo_adr <= s_master_out.adr;
wbmo_sel <= s_master_out.sel;
wbmo_cyc <= s_master_out.cyc;
s_master_in.dat <= wbmo_datrd;
s_master_in.ack <= wbmo_ack;
s_master_in.err <= wbmo_err;
s_master_in.stall <= wbmo_stall;
-- main : process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(reset_n = '0') then
-- s_master_in.stall <= '0';
-- s_master_in.ack <= '0';
-- s_master_in.err <= '0';
-- reg <= (others => '0');
-- else
-- s_master_in.ack <= '0';
-- if((s_master_out.cyc and s_master_out.stb and not s_master_in.stall) = '1') then
-- if(s_master_out.we = '1') then
-- reg <= s_master_out.dat;
-- end if;
-- s_master_in.ack <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
end architecture;
| bsd-3-clause |
mkreider/cocotb2 | tests/designs/viterbi_decoder_axi4s/packages/pkg_param.vhd | 7 | 2076 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Parameters
--! @author Markus Fehrenz
--! @date 2011/07/01
--!
--! @details This is the configuration file of the Viterbi decoder.
--! Any changes for parameters should be done here.
--! Changing parameters somewhere else may result in a malicious
--! behavior.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_param is
-----------------------------------
-- Convolutional Code Parameters --
-----------------------------------
--
-- Set the number of parity values
-- This has to correspond to PARITY_POLYNOMIALS
--
constant NUMBER_PARITY_BITS : natural := 2;
type t_parity is array (NUMBER_PARITY_BITS - 1 downto 0) of natural;
--
-- Set parity polynoms in decimal notation
-- NUMBER_PARITY_BITS has to correspond to the number of elements
-- Examples: WiFi : [121,91] or [121,91,101]
-- CDMA : [491,369] or [367,435,369] or [501,441,331,315]
-- GSM : [27,19] or [27,21,31]
-- DAB : [91,121,101,91]
-- WiMAX: [91,121,117]
--
constant PARITY_POLYNOMIALS : t_parity := (121,91);
--
-- Set a recursive polynomial
-- Set to 0 if no recursion is used
-- Setting this arbitrary may result in a worse error correction ability
--
constant FEEDBACK_POLYNOMIAL : natural := 0;
-----------------------------
-- Architecture Parameters --
-----------------------------
--
-- Set bit width of LLR input
-- Recommended values: 3 or 4
--
constant BW_LLR_INPUT : natural := 4;
--
-- Set the maximum window length which shall be allowed at runtime.
-- Recommended: at least 6 * constraint length
--
constant MAX_WINDOW_LENGTH : natural := 96;
--
-- Set to 'true' if distributed RAM shall be used
-- Set to 'false' if block RAM shall be used
--
constant DISTRIBUTED_RAM : boolean := true;
end package pkg_param;
| bsd-3-clause |
gujiman/ace-builds | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/transloop.vhdl | 1 | 5990 | --
-- Transceiver Loop
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.verif.all;
entity TransLoop is
generic (
DBYTES : positive:=4; -- Data bytes
TSIZE : positive:=1e4; -- Total size
FSIZE : positive:=2048 -- Frame size
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
tx_data_o : out std_logic_vector(DBYTES*8-1 downto 0);
tx_isk_o : out std_logic_vector(DBYTES-1 downto 0);
tx_ready_i : in std_logic;
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
rx_isk_i : in std_logic_vector(DBYTES-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0);
rx_finish_o : out std_logic;
rx_cycles_o : out std_logic_vector(31 downto 0)
);
end entity TransLoop;
architecture RTL of TransLoop is
constant K28_5 : std_logic_vector(7 downto 0):=x"BC";
constant K28_1 : std_logic_vector(7 downto 0):=x"3C";
constant DWIDTH : positive:=DBYTES*8;
signal rx_data, tx_data : std_logic_vector(DWIDTH-1 downto 0);
signal rx_stb, tx_stb : std_logic;
signal rx_cnt, tx_cnt : unsigned(DWIDTH-1 downto 0);
signal rx_cycles : unsigned(31 downto 0);
type state_t is (IDLE, STROBE, ACK, TRANSFER, GAP, FINISH);
signal tx_state, rx_state : state_t:=IDLE;
function repeat (value: std_logic_vector; num: positive) return std_logic_vector is
variable retval : std_logic_vector(num*8-1 downto 0);
begin
for i in 1 to num loop
retval(i*8-1 downto (i-1)*8):=value;
end loop;
return retval;
end repeat;
constant tied_to_vcc : std_logic_vector(DWIDTH-1 downto 0):=(others => '1');
constant tied_to_gnd : std_logic_vector(DWIDTH-1 downto 0):=(others => '0');
begin
loop_i: LoopCheck
generic map (DWIDTH => DWIDTH)
port map(
-- TX side
tx_clk_i => tx_clk_i,
tx_rst_i => tx_rst_i,
tx_stb_i => tx_stb,
tx_data_i => tx_data_i,
tx_data_o => tx_data,
-- RX side
rx_clk_i => rx_clk_i,
rx_rst_i => rx_rst_i,
rx_stb_i => rx_stb,
rx_data_i => rx_data,
rx_errors_o => rx_errors_o
);
tx_fsm: process(tx_clk_i) is
begin
if rising_edge(tx_clk_i) then
if tx_rst_i='1' then
tx_state <= IDLE;
tx_isk_o <= (others => '0');
tx_data_o <= (others => '0');
tx_cnt <= (others => '0');
tx_stb <= '0';
else
case tx_state is
when IDLE =>
if tx_ready_i='1' then
tx_state <= STROBE;
end if;
when STROBE =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_5,DBYTES);
tx_state <= ACK;
when ACK =>
if rx_data_i=repeat(K28_5,DBYTES) and rx_isk_i=tied_to_vcc(DBYTES-1 downto 0) then
tx_state <= TRANSFER;
tx_stb <= '1';
end if;
when TRANSFER =>
tx_isk_o <= (others => '0');
tx_data_o <= tx_data;
tx_cnt <= tx_cnt+1;
if tx_cnt=TSIZE-1 then
tx_stb <= '0';
tx_state <= FINISH;
elsif (tx_cnt mod FSIZE = FSIZE-1) then
tx_state <= GAP;
tx_stb <= '0';
end if;
when GAP =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_1,DBYTES);
tx_state <= TRANSFER;
tx_stb <= '1';
when FINISH =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_5,DBYTES);
when others =>
tx_state <= IDLE;
end case;
end if;
end if;
end process tx_fsm;
rx_fsm: process(rx_clk_i) is
begin
if rising_edge(rx_clk_i) then
rx_finish_o <= '0';
if rx_rst_i='1' then
rx_state <= IDLE;
rx_cnt <= (others => '0');
else
case rx_state is
when IDLE =>
if rx_data_i=repeat(K28_5,DBYTES) and rx_isk_i=tied_to_vcc(DBYTES-1 downto 0) then
rx_state <= ACK;
end if;
when ACK =>
rx_state <= TRANSFER;
rx_cycles <= (others => '0');
when TRANSFER =>
rx_cycles <= rx_cycles + 1;
if rx_isk_i=tied_to_gnd(DBYTES-1 downto 0) then
rx_data <= rx_data_i;
rx_stb <= '1';
rx_cnt <= rx_cnt + 1;
else
rx_stb <= '0';
if rx_cnt>0 and rx_data_i=repeat(K28_5,DBYTES) then
rx_state <= FINISH;
rx_finish_o <= '1';
end if;
end if;
when FINISH =>
rx_finish_o <= '1';
when others =>
rx_state <= IDLE;
end case;
end if;
end if;
end process rx_fsm;
rx_cycles_o <= std_logic_vector(rx_cycles);
end architecture RTL;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_lib | vhdl/verif/testbench/transloop_tb.vhdl | 1 | 1810 | --
-- Transceiver Loop Testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Verif.all;
use FPGALIB.Simul.all;
entity TransLoop_Tb is
end entity TransLoop_Tb;
architecture Test of TransLoop_Tb is
constant FREQUENCY : positive:=150e6;
signal clk, rst : std_logic;
signal stop : boolean;
-- dut
signal ready : std_logic;
signal data : std_logic_vector(31 downto 0);
signal isk : std_logic_vector(3 downto 0);
signal errors : std_logic_vector(4 downto 0);
signal finish : std_logic;
begin
do_clk: Clock
generic map(FREQUENCY => FREQUENCY)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
dut: TransLoop
port map(
-- TX side
tx_clk_i => clk,
tx_rst_i => rst,
tx_data_i => (others => '0'),
tx_data_o => data,
tx_isk_o => isk,
tx_ready_i => ready,
-- RX side
rx_clk_i => clk,
rx_rst_i => rst,
rx_data_i => data,
rx_isk_i => isk,
rx_errors_o => errors,
rx_finish_o => finish,
rx_cycles_o => open
);
do_run: process
begin
ready <= '0';
wait until rising_edge(clk) and rst='0';
ready <= '1';
wait until rising_edge(clk);
ready <= '0';
wait until rising_edge(clk) and finish='1';
assert errors="00000"
report "ERROR: there were errors ("&to_str(errors)&")." severity failure;
stop <= TRUE;
wait;
end process do_run;
end architecture Test;
| bsd-3-clause |
sonologic/gmzpu | vhdl/roms/dmips_dbram.vhdl | 1 | 105913 | ------------------------------------------------------------------------------
---- ----
---- Dual Port RAM that maps to a Xilinx BRAM ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a program+data memory for the ZPU. It maps to a Xilinx BRAM ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: DualPortRAM(Xilinx) (Entity and architecture) ----
---- File name: rom.in.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity DualPortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
-- Port A
a_we_i : in std_logic;
a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
a_write_i : in unsigned(WORD_SIZE-1 downto 0);
a_read_o : out unsigned(WORD_SIZE-1 downto 0);
-- Port B
b_we_i : in std_logic;
b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
b_write_i : in unsigned(WORD_SIZE-1 downto 0);
b_read_o : out unsigned(WORD_SIZE-1 downto 0));
end entity DualPortRAM;
architecture Xilinx of DualPortRAM is
type ram_type is array(natural range 0 to ((2**BRAM_W)/4)-1) of unsigned(WORD_SIZE-1 downto 0);
shared variable ram : ram_type:=
(
0 => x"0b0b0b0b",
1 => x"82700b0b",
2 => x"80f8ec0c",
3 => x"3a0b0b80",
4 => x"e7ea0400",
5 => x"00000000",
6 => x"00000000",
7 => x"00000000",
8 => x"80088408",
9 => x"88080b0b",
10 => x"80e8b72d",
11 => x"880c840c",
12 => x"800c0400",
13 => x"00000000",
14 => x"00000000",
15 => x"00000000",
16 => x"71fd0608",
17 => x"72830609",
18 => x"81058205",
19 => x"832b2a83",
20 => x"ffff0652",
21 => x"04000000",
22 => x"00000000",
23 => x"00000000",
24 => x"71fd0608",
25 => x"83ffff73",
26 => x"83060981",
27 => x"05820583",
28 => x"2b2b0906",
29 => x"7383ffff",
30 => x"0b0b0b0b",
31 => x"83a70400",
32 => x"72098105",
33 => x"72057373",
34 => x"09060906",
35 => x"73097306",
36 => x"070a8106",
37 => x"53510400",
38 => x"00000000",
39 => x"00000000",
40 => x"72722473",
41 => x"732e0753",
42 => x"51040000",
43 => x"00000000",
44 => x"00000000",
45 => x"00000000",
46 => x"00000000",
47 => x"00000000",
48 => x"71737109",
49 => x"71068106",
50 => x"30720a10",
51 => x"0a720a10",
52 => x"0a31050a",
53 => x"81065151",
54 => x"53510400",
55 => x"00000000",
56 => x"72722673",
57 => x"732e0753",
58 => x"51040000",
59 => x"00000000",
60 => x"00000000",
61 => x"00000000",
62 => x"00000000",
63 => x"00000000",
64 => x"00000000",
65 => x"00000000",
66 => x"00000000",
67 => x"00000000",
68 => x"00000000",
69 => x"00000000",
70 => x"00000000",
71 => x"00000000",
72 => x"0b0b0b88",
73 => x"c4040000",
74 => x"00000000",
75 => x"00000000",
76 => x"00000000",
77 => x"00000000",
78 => x"00000000",
79 => x"00000000",
80 => x"720a722b",
81 => x"0a535104",
82 => x"00000000",
83 => x"00000000",
84 => x"00000000",
85 => x"00000000",
86 => x"00000000",
87 => x"00000000",
88 => x"72729f06",
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4170 => x"00000000",
4171 => x"00000000",
4172 => x"00000000",
4173 => x"00000000",
4174 => x"00000000",
4175 => x"00000000",
4176 => x"00000000",
4177 => x"00000000",
4178 => x"00000000",
4179 => x"00000000",
4180 => x"00000000",
4181 => x"00000000",
4182 => x"00000000",
4183 => x"00000000",
4184 => x"00000000",
4185 => x"00000000",
4186 => x"00000000",
4187 => x"00000000",
4188 => x"00000000",
4189 => x"00000001",
4190 => x"330eabcd",
4191 => x"1234e66d",
4192 => x"deec0005",
4193 => x"000b0000",
4194 => x"00000000",
4195 => x"00000000",
4196 => x"00000000",
4197 => x"00000000",
4198 => x"00000000",
4199 => x"00000000",
4200 => x"00000000",
4201 => x"00000000",
4202 => x"00000000",
4203 => x"00000000",
4204 => x"00000000",
4205 => x"00000000",
4206 => x"00000000",
4207 => x"00000000",
4208 => x"00000000",
4209 => x"00000000",
4210 => x"00000000",
4211 => x"00000000",
4212 => x"00000000",
4213 => x"00000000",
4214 => x"00000000",
4215 => x"00000000",
4216 => x"00000000",
4217 => x"00000000",
4218 => x"00000000",
4219 => x"00000000",
4220 => x"00000000",
4221 => x"00000000",
4222 => x"00000000",
4223 => x"00000000",
4224 => x"00000000",
4225 => x"00000000",
4226 => x"00000000",
4227 => x"00000000",
4228 => x"00000000",
4229 => x"00000000",
4230 => x"00000000",
4231 => x"00000000",
4232 => x"00000000",
4233 => x"00000000",
4234 => x"00000000",
4235 => x"00000000",
4236 => x"00000000",
4237 => x"00000000",
4238 => x"00000000",
4239 => x"00000000",
4240 => x"00000000",
4241 => x"00000000",
4242 => x"00000000",
4243 => x"00000000",
4244 => x"00000000",
4245 => x"00000000",
4246 => x"00000000",
4247 => x"00000000",
4248 => x"00000000",
4249 => x"00000000",
4250 => x"00000000",
4251 => x"00000000",
4252 => x"00000000",
4253 => x"00000000",
4254 => x"00000000",
4255 => x"00000000",
4256 => x"00000000",
4257 => x"00000000",
4258 => x"00000000",
4259 => x"00000000",
4260 => x"00000000",
4261 => x"00000000",
4262 => x"00000000",
4263 => x"00000000",
4264 => x"00000000",
4265 => x"00000000",
4266 => x"00000000",
4267 => x"00000000",
4268 => x"00000000",
4269 => x"00000000",
4270 => x"00000000",
4271 => x"00000000",
4272 => x"00000000",
4273 => x"00000000",
4274 => x"00000000",
4275 => x"00000000",
4276 => x"00000000",
4277 => x"00000000",
4278 => x"00000000",
4279 => x"00000000",
4280 => x"00000000",
4281 => x"00000000",
4282 => x"00000000",
4283 => x"00000000",
4284 => x"00000000",
4285 => x"00000000",
4286 => x"00000000",
4287 => x"00000000",
4288 => x"00000000",
4289 => x"00000000",
4290 => x"00000000",
4291 => x"00000000",
4292 => x"00000000",
4293 => x"00000000",
4294 => x"00000000",
4295 => x"00000000",
4296 => x"00000000",
4297 => x"00000000",
4298 => x"00000000",
4299 => x"00000000",
4300 => x"00000000",
4301 => x"00000000",
4302 => x"00000000",
4303 => x"00000000",
4304 => x"00000000",
4305 => x"00000000",
4306 => x"00000000",
4307 => x"00000000",
4308 => x"00000000",
4309 => x"00000000",
4310 => x"00000000",
4311 => x"00000000",
4312 => x"00000000",
4313 => x"00000000",
4314 => x"00000000",
4315 => x"00000000",
4316 => x"00000000",
4317 => x"00000000",
4318 => x"00000000",
4319 => x"00000000",
4320 => x"00000000",
4321 => x"00000000",
4322 => x"00000000",
4323 => x"00000000",
4324 => x"00000000",
4325 => x"00000000",
4326 => x"00000000",
4327 => x"00000000",
4328 => x"00000000",
4329 => x"00000000",
4330 => x"00000000",
4331 => x"00000000",
4332 => x"00000000",
4333 => x"00000000",
4334 => x"00000000",
4335 => x"00000000",
4336 => x"00000000",
4337 => x"00000000",
4338 => x"00000000",
4339 => x"00000000",
4340 => x"00000000",
4341 => x"00000000",
4342 => x"00000000",
4343 => x"00000000",
4344 => x"00000000",
4345 => x"00000000",
4346 => x"00000000",
4347 => x"00000000",
4348 => x"00000000",
4349 => x"00000000",
4350 => x"00000000",
4351 => x"00000000",
4352 => x"00000000",
4353 => x"00000000",
4354 => x"00000000",
4355 => x"00000000",
4356 => x"00000000",
4357 => x"00000000",
4358 => x"00000000",
4359 => x"00000000",
4360 => x"00000000",
4361 => x"00000000",
4362 => x"00000000",
4363 => x"00000000",
4364 => x"00000000",
4365 => x"00000000",
4366 => x"00000000",
4367 => x"00000000",
4368 => x"00000000",
4369 => x"00000000",
4370 => x"00003c4c",
4371 => x"ffffffff",
4372 => x"00000000",
4373 => x"ffffffff",
4374 => x"00000000",
4375 => x"00000000",
others => x"00000000"
);
begin
do_port_a:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
if (a_we_i='1') and (b_we_i='1') and (a_addr_i=b_addr_i) and (a_write_i/=b_write_i) then
report "DualPortRAM write collision" severity failure;
end if;
iaddr:=to_integer(a_addr_i);
if a_we_i='1' then
ram(iaddr):=a_write_i;
-- Write First mode
a_read_o <= a_write_i;
else
a_read_o <= ram(iaddr);
end if;
end if;
end process do_port_a;
do_port_b:
process (clk_i)
variable iaddr : integer;
begin
if rising_edge(clk_i) then
iaddr:=to_integer(b_addr_i);
if b_we_i='1' then
ram(iaddr):=b_write_i;
b_read_o <= b_write_i;
else
b_read_o <= ram(iaddr);
end if;
end if;
end process do_port_b;
end architecture Xilinx; -- Entity: DualPortRAM
| bsd-3-clause |
sonologic/gmzpu | vhdl/devices/timer.vhdl | 1 | 4770 | ------------------------------------------------------------------------------
---- ----
---- 64 bits clock counter ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a peripheral used by the PHI I/O layout. It just counts the ----
---- elapsed number of clocks. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Timer(Behave) (Entity and architecture) ----
---- File name: timer.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Timer is
port(
clk_i : in std_logic;
reset_i : in std_logic;
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned(0 downto 0);
data_o : out unsigned(31 downto 0));
end entity Timer;
architecture Behave of Timer is
signal sample : std_logic;
signal reset : std_logic;
signal cnt : unsigned(63 downto 0);
signal cnt_smp : unsigned(63 downto 0);
begin
reset <= '1' when (we_i='1' and data_i(0)='1') else '0';
sample <= '1' when (we_i='1' and data_i(1)='1') else '0';
-- Carry generation
do_timer:
process (clk_i)
begin
if rising_edge(clk_i) then
if reset_i='1' or reset='1' then
cnt <= (others => '0');
cnt_smp <= (others => '0');
else
cnt <= cnt+1;
if sample='1' then
-- report "sampling" severity failure;
cnt_smp <= cnt;
end if;
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process do_timer;
data_o <= cnt_smp(31 downto 0) when to_01(addr_i)="0" else
cnt_smp(63 downto 32);
end architecture Behave; -- Entity: Timer
| bsd-3-clause |
ashmind/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
sonologic/gmzpu | vhdl/ZetaIO/interrupt/test/interrupt_line_tb.vhdl | 1 | 8368 | ------------------------------------------------------------------------------
---- ----
---- gmzpu interrupt line component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.pic;
entity interrupt_line_TB is
end entity interrupt_line_TB;
architecture Behave of interrupt_line_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
component interrupt_line is
port (
clk_i : in std_logic;
int_i : in std_logic;
irq_o : out std_logic;
icr_o : out std_logic;
icr_i : in std_logic;
imr_i : in std_logic;
ier_i : in std_logic;
itr_i : in std_logic;
we_i : in std_logic
);
end component interrupt_line;
type sample is record
-- inputs
int_i : std_logic;
icr_i : std_logic;
imr_i : std_logic;
ier_i : std_logic;
itr_i : std_logic;
we_i : std_logic;
-- outputs
irq_o : std_logic;
icr_o : std_logic;
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- int icr imr ier itr we irq icr
-- reset
('0','0','0','0','0','1', '0','0'),
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
-- assert imr, then int_i
('0','0','1','0','0','0', '0','0'),
('1','0','1','0','0','0', '1','1'),
('0','0','1','0','0','0', '1','1'),
('0','0','1','0','0','0', '1','1'),
('0','0','0','0','0','1', '0','0'),
('0','0','0','0','0','0', '0','0'),
-- rising edge
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','1', '0','0'),
('1','0','0','0','0','0', '0','0'),
('1','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
-- falling edge
('0','0','0','1','0','0', '0','0'),
('0','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('0','0','0','1','0','0', '0','1'),
('0','0','0','1','0','0', '0','1'),
('0','0','0','1','0','1', '0','0'),
('0','0','0','1','0','0', '0','0'),
('0','0','0','1','0','0', '0','0'),
-- int icr imr ier itr we irq icr
-- level trig
('0','0','0','0','1','0', '0','0'),
('0','0','0','0','1','0', '0','0'),
('1','0','0','0','1','0', '0','1'),
('1','0','0','0','1','0', '0','1'),
('1','0','0','0','1','0', '0','1'),
('0','0','0','0','1','0', '0','0'),
('0','0','0','0','1','0', '0','0'),
-- terminate
('0','0','0','0','0','0', '0','0')
);
signal clk : std_logic;
signal int_i : std_logic;
signal icr_i : std_logic;
signal imr_i : std_logic;
signal ier_i : std_logic;
signal itr_i : std_logic;
signal we_i : std_logic;
signal irq_o : std_logic;
signal icr_o : std_logic;
signal valid : std_logic;
begin
line : interrupt_line
port map(int_i => int_i, icr_i => icr_i, imr_i => imr_i, ier_i => ier_i, itr_i => itr_i, we_i => we_i,
irq_o => irq_o, icr_o => icr_o,
clk_i => clk);
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
int_i <= test_data(i).int_i;
icr_i <= test_data(i).icr_i;
imr_i <= test_data(i).imr_i;
ier_i <= test_data(i).ier_i;
itr_i <= test_data(i).itr_i;
we_i <= test_data(i).we_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
valid <= '1';
if irq_o/=test_data(i).irq_o then
valid <= 'Z';
end if;
if icr_o/=test_data(i).icr_o then
valid <= 'Z';
end if;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity error;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
| bsd-3-clause |
sonologic/gmzpu | vhdl/roms/rom_pkg.vhdl | 1 | 4618 | ------------------------------------------------------------------------------
---- ----
---- ZPU memories package ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- This is a package with the memories used for the ZPU core. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_memory (Package) ----
---- File name: rom_pkg.vhdl (template used) ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package zpu_memory is
component DualPortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
-- Port A
a_we_i : in std_logic;
a_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
a_write_i : in unsigned(WORD_SIZE-1 downto 0);
a_read_o : out unsigned(WORD_SIZE-1 downto 0);
-- Port B
b_we_i : in std_logic;
b_addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
b_write_i : in unsigned(WORD_SIZE-1 downto 0);
b_read_o : out unsigned(WORD_SIZE-1 downto 0));
end component DualPortRAM;
component SinglePortRAM is
generic(
WORD_SIZE : integer:=32; -- Word Size 16/32
BYTE_BITS : integer:=2; -- Bits used to address bytes
BRAM_W : integer:=15); -- Address Width
port(
clk_i : in std_logic;
we_i : in std_logic;
re_i : in std_logic;
addr_i : in unsigned(BRAM_W-1 downto BYTE_BITS);
write_i : in unsigned(WORD_SIZE-1 downto 0);
read_o : out unsigned(WORD_SIZE-1 downto 0);
busy_o : out std_logic);
end component SinglePortRAM;
end package zpu_memory;
| bsd-3-clause |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/checker.vhd | 6 | 5607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.BMG_TB_PKG.ALL;
ENTITY CHECKER IS
GENERIC ( WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END CHECKER;
ARCHITECTURE CHECKER_ARCH OF CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| bsd-3-clause |
itsff/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
paladox/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
Xilinx/PYNQ | boards/ip/dvi2rgb_v1_7/src/GlitchFilter.vhd | 15 | 3919 | -------------------------------------------------------------------------------
--
-- File: GlitchFilter.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 22 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module filters any pulses on sIn lasting less than the number of
-- periods specified in kNoOfPeriodsToFilter. The output sOut will be
-- delayed by kNoOfPeriodsToFilter cycles, but glitch-free.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GlitchFilter is
Generic (
kNoOfPeriodsToFilter : natural);
Port (
SampleClk : in STD_LOGIC;
sIn : in STD_LOGIC;
sOut : out STD_LOGIC;
sRst : in STD_LOGIC);
end GlitchFilter;
architecture Behavioral of GlitchFilter is
signal cntPeriods : natural range 0 to kNoOfPeriodsToFilter - 1 := kNoOfPeriodsToFilter - 1;
signal sIn_q : std_logic;
begin
Bypass: if kNoOfPeriodsToFilter = 0 generate
sOut <= sIn;
end generate Bypass;
Filter: if kNoOfPeriodsToFilter > 0 generate
process (SampleClk)
begin
if Rising_Edge(SampleClk) then
sIn_q <= sIn;
if (cntPeriods = 0) then
sOut <= sIn_q;
end if;
end if;
end process;
PeriodCounter: process (SampleClk)
begin
if Rising_Edge(SampleClk) then
if (sIn_q /= sIn or sRst = '1') then --edge detected
cntPeriods <= kNoOfPeriodsToFilter - 1; --reset counter
elsif (cntPeriods /= 0) then
cntPeriods <= cntPeriods - 1; --count down
end if;
end if;
end process PeriodCounter;
end generate Filter;
end Behavioral;
| bsd-3-clause |
Xilinx/PYNQ | boards/ip/rgb2dvi_v1_2/src/SyncAsync.vhd | 34 | 3727 | -------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
| bsd-3-clause |
Xilinx/PYNQ | boards/ip/dvi2rgb_v1_7/src/SyncAsync.vhd | 34 | 3727 | -------------------------------------------------------------------------------
--
-- File: SyncAsync.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes the asynchronous signal (aIn) with the OutClk clock
-- domain and provides it on oOut. The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous reset (aReset) is always active-high.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncAsync is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aReset : in STD_LOGIC; -- active-high asynchronous reset
aIn : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
end SyncAsync;
architecture Behavioral of SyncAsync is
signal oSyncStages : std_logic_vector(kStages-1 downto 0) := (others => kResetTo);
attribute ASYNC_REG : string;
attribute ASYNC_REG of oSyncStages: signal is "TRUE";
begin
Sync: process (OutClk, aReset)
begin
if (aReset = '1') then
oSyncStages <= (others => kResetTo);
elsif Rising_Edge(OutClk) then
oSyncStages <= oSyncStages(oSyncStages'high-1 downto 0) & aIn;
end if;
end process Sync;
oOut <= oSyncStages(oSyncStages'high);
end Behavioral;
| bsd-3-clause |
larskuhtz/MoCS | vhdl/countdown_tb.vhdl | 1 | 1603 | -- *** MOCS-COPYRIGHT-NOTICE-BEGIN ***
--
-- This copyright notice is auto-generated by ./add-copyright-notice.
-- Additional copyright notices must be added below the last line of this notice.
--
-- MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/): "vhdl/countdown_tb.vhdl".
-- The content of this file is copyright of Saarland University -
-- Copyright (C) 2009 Saarland University, Reactive Systems Group, Lars Kuhtz.
--
-- This file is part of MoCS (https://lewis.cs.uni-saarland.de/tools/mocs/).
--
-- License: three-clause BSD style license.
-- The license text can be found in the file LICENSE.
--
-- *** MOCS-COPYRIGHT-NOTICE-END ***
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.countdown;
entity countdown_tb is
end countdown_tb;
architecture Behavioral of countdown_tb is
constant max : Integer := 5;
signal CLOCK, o : STD_LOGIC;
signal ticks : Integer := 0; -- interal
begin
process
begin
CLOCK <= '1'; wait for 5 ns;
CLOCK <= '0'; wait for 5 ns;
end process;
countdown0 : entity work.countdown(Behavioral)
generic map(max => max)
port map(CLOCK,o);
check0 : process(CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
ticks <= ticks + 1;
end if;
end process;
check1 : process(CLOCK)
begin
assert (ticks < max-1) xor (o = '1') report "counter failed";
assert (0 = 1) report "ticks = " & integer'image(ticks) & ", o = " & std_logic'image(o);
end process;
end Behavioral;
| bsd-3-clause |
VectorBlox/risc-v | ip/orca/hdl/cache_mux.vhd | 1 | 24104 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
--This OIMM Mux can be configured with or without multiple read support. If
--MAX_OUTSTANDING_READS is 1, then it is the responsibility of the requester to
--not issue a read request while a current read request is pending but the
--readdatavalid signal has not been asserted. If turned on then the
--MAX_OUTSTANDING_READS generic sets the number of outstanding reads that can
--be in flight on any one interface; all reads on one interface must finish
--before reads on another interface can start. MAX_OUTSTANDING_READS should be
--set to a power of 2 minus 1 (1,3,7,15,etc.) normally as numbers between those
--will use the same amount of resources as the next highest power of 2 minus 1.
entity cache_mux is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
MAX_OUTSTANDING_READS : positive;
AUX_MEMORY_REGIONS : natural range 0 to 4;
AMR0_ADDR_BASE : std_logic_vector(31 downto 0);
AMR0_ADDR_LAST : std_logic_vector(31 downto 0);
UC_MEMORY_REGIONS : natural range 0 to 4;
UMR0_ADDR_BASE : std_logic_vector(31 downto 0);
UMR0_ADDR_LAST : std_logic_vector(31 downto 0);
CACHE_SIZE : natural;
CACHE_LINE_SIZE : positive range 16 to 256;
INTERNAL_REQUEST_REGISTER : request_register_type;
INTERNAL_RETURN_REGISTER : boolean;
UC_REQUEST_REGISTER : request_register_type;
UC_RETURN_REGISTER : boolean;
AUX_REQUEST_REGISTER : request_register_type;
AUX_RETURN_REGISTER : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
amr_base_addrs : in std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
amr_last_addrs : in std_logic_vector((imax(AUX_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
umr_base_addrs : in std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
umr_last_addrs : in std_logic_vector((imax(UC_MEMORY_REGIONS, 1)*ADDRESS_WIDTH)-1 downto 0);
internal_register_idle : out std_logic;
external_registers_idle : out std_logic;
--ORCA-internal memory-mapped slave
oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0) := (others => '1');
oimm_requestvalid : in std_logic;
oimm_readnotwrite : in std_logic := '1';
oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '-');
oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
oimm_readdatavalid : out std_logic;
oimm_waitrequest : out std_logic;
--Cache interface ORCA-internal memory-mapped master
cacheint_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
cacheint_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
cacheint_oimm_requestvalid : out std_logic;
cacheint_oimm_readnotwrite : out std_logic;
cacheint_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
cacheint_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
cacheint_oimm_readdatavalid : in std_logic;
cacheint_oimm_waitrequest : in std_logic;
--Uncached ORCA-internal memory-mapped master
uc_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
uc_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
uc_oimm_requestvalid : out std_logic;
uc_oimm_readnotwrite : out std_logic;
uc_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
uc_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
uc_oimm_readdatavalid : in std_logic;
uc_oimm_waitrequest : in std_logic;
--Tightly-coupled memory ORCA-internal memory-mapped master
aux_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
aux_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
aux_oimm_requestvalid : out std_logic;
aux_oimm_readnotwrite : out std_logic;
aux_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
aux_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
aux_oimm_readdatavalid : in std_logic;
aux_oimm_waitrequest : in std_logic
);
end entity cache_mux;
architecture rtl of cache_mux is
signal internal_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal internal_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal internal_oimm_requestvalid : std_logic;
signal internal_oimm_readnotwrite : std_logic;
signal internal_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_oimm_readdatavalid : std_logic;
signal internal_oimm_waitrequest : std_logic;
signal c_outstanding_reads : unsigned(log2(MAX_OUTSTANDING_READS+1)-1 downto 0);
signal uc_outstanding_reads : unsigned(log2(MAX_OUTSTANDING_READS+1)-1 downto 0);
signal aux_outstanding_reads : unsigned(log2(MAX_OUTSTANDING_READS+1)-1 downto 0);
signal c_zero_outstanding_reads : std_logic;
signal uc_zero_outstanding_reads : std_logic;
signal aux_zero_outstanding_reads : std_logic;
signal c_max_outstanding_reads : std_logic;
signal uc_max_outstanding_reads : std_logic;
signal aux_max_outstanding_reads : std_logic;
type address_vector is array (natural range <>) of unsigned(ADDRESS_WIDTH-1 downto 0);
signal amr_base_addr : address_vector(imax(AUX_MEMORY_REGIONS, 1)-1 downto 0);
signal amr_last_addr : address_vector(imax(AUX_MEMORY_REGIONS, 1)-1 downto 0);
signal amr_address_match : std_logic_vector(imax(AUX_MEMORY_REGIONS, 1)-1 downto 0);
signal umr_base_addr : address_vector(imax(UC_MEMORY_REGIONS, 1)-1 downto 0);
signal umr_last_addr : address_vector(imax(UC_MEMORY_REGIONS, 1)-1 downto 0);
signal umr_address_match : std_logic_vector(imax(UC_MEMORY_REGIONS, 1)-1 downto 0);
signal c_select : std_logic;
signal uc_select : std_logic;
signal aux_select : std_logic;
signal read_stall : std_logic;
signal internal_uc_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal internal_uc_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal internal_uc_oimm_requestvalid : std_logic;
signal internal_uc_oimm_readnotwrite : std_logic;
signal internal_uc_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_uc_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_uc_oimm_readdatavalid : std_logic;
signal internal_uc_oimm_waitrequest : std_logic;
signal uc_register_idle : std_logic;
signal internal_aux_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal internal_aux_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal internal_aux_oimm_requestvalid : std_logic;
signal internal_aux_oimm_readnotwrite : std_logic;
signal internal_aux_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_aux_oimm_readdata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal internal_aux_oimm_readdatavalid : std_logic;
signal internal_aux_oimm_waitrequest : std_logic;
signal aux_register_idle : std_logic;
begin
-----------------------------------------------------------------------------
-- Optional Internal OIMM Register
-----------------------------------------------------------------------------
internal_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
REQUEST_REGISTER => INTERNAL_REQUEST_REGISTER,
RETURN_REGISTER => INTERNAL_RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => internal_register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => oimm_address,
slave_oimm_byteenable => oimm_byteenable,
slave_oimm_requestvalid => oimm_requestvalid,
slave_oimm_readnotwrite => oimm_readnotwrite,
slave_oimm_writedata => oimm_writedata,
slave_oimm_readdata => oimm_readdata,
slave_oimm_readdatavalid => oimm_readdatavalid,
slave_oimm_waitrequest => oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => internal_oimm_address,
master_oimm_byteenable => internal_oimm_byteenable,
master_oimm_requestvalid => internal_oimm_requestvalid,
master_oimm_readnotwrite => internal_oimm_readnotwrite,
master_oimm_writedata => internal_oimm_writedata,
master_oimm_readdata => internal_oimm_readdata,
master_oimm_readdatavalid => internal_oimm_readdatavalid,
master_oimm_waitrequest => internal_oimm_waitrequest
);
cacheint_oimm_address <= internal_oimm_address;
cacheint_oimm_byteenable <= internal_oimm_byteenable;
cacheint_oimm_writedata <= internal_oimm_writedata;
internal_uc_oimm_address <= internal_oimm_address;
internal_uc_oimm_byteenable <= internal_oimm_byteenable;
internal_uc_oimm_writedata <= internal_oimm_writedata;
internal_aux_oimm_address <= internal_oimm_address;
internal_aux_oimm_byteenable <= internal_oimm_byteenable;
internal_aux_oimm_writedata <= internal_oimm_writedata;
amr_gen : for gregister in imax(AUX_MEMORY_REGIONS, 1)-1 downto 0 generate
amr_base_addr(gregister) <=
unsigned(amr_base_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
amr_last_addr(gregister) <=
unsigned(amr_last_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
amr_address_match(gregister) <=
'1' when ((unsigned(internal_oimm_address) >= amr_base_addr(gregister)) and
(unsigned(internal_oimm_address) <= amr_last_addr(gregister))) else
'0';
end generate amr_gen;
umr_gen : for gregister in imax(UC_MEMORY_REGIONS, 1)-1 downto 0 generate
umr_base_addr(gregister) <=
unsigned(umr_base_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
umr_last_addr(gregister) <=
unsigned(umr_last_addrs(((gregister+1)*ADDRESS_WIDTH)-1 downto gregister*ADDRESS_WIDTH));
umr_address_match(gregister) <=
'1' when ((unsigned(internal_oimm_address) >= umr_base_addr(gregister)) and
(unsigned(internal_oimm_address) <= umr_last_addr(gregister))) else
'0';
end generate umr_gen;
--Generate control signals depending on which interfaces are enabled and if
--the address ranges overalp. Cache has all unspecified addresses. If AUX
--and UC overlap use AUX.
no_aux_gen : if AUX_MEMORY_REGIONS = 0 generate
aux_select <= '0';
no_uc_gen : if UC_MEMORY_REGIONS = 0 generate
uc_select <= '0';
external_registers_idle <= '1';
no_c_gen : if CACHE_SIZE = 0 generate
c_select <= '0';
internal_oimm_readdata <= (others => '-');
internal_oimm_readdatavalid <= '0';
assert true report
"Error; Cache is disabled (CACHE_SIZE = 0), UC interface is disabled (UC_MEMORY_REGIONS = 0), and AUX interface is disabled (AUX_MEMORY_REGIONS = 0). At least one interface must be enabled."
severity failure;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
c_select <= '1';
internal_oimm_readdata <= cacheint_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid;
end generate has_c_gen;
end generate no_uc_gen;
has_uc_gen : if UC_MEMORY_REGIONS /= 0 generate
external_registers_idle <= uc_register_idle;
no_c_gen : if CACHE_SIZE = 0 generate
c_select <= '0';
uc_select <= '1';
internal_oimm_readdata <= internal_uc_oimm_readdata;
internal_oimm_readdatavalid <= internal_uc_oimm_readdatavalid;
assert not ((unsigned(UMR0_ADDR_BASE) /= to_unsigned(0, UMR0_ADDR_BASE'length)) or
(signed(UMR0_ADDR_LAST) /= to_signed(-1, UMR0_ADDR_LAST'length))) report
"Warning; Cache is disabled (CACHE_SIZE = 0) and AUX interface is disabled (AUX_MEMORY_REGIONS = 0) but UMR0 address range does not encompass the full address range. All accesses will go to UC interface, even those not in the UMR0 address range."
severity note;
assert UC_MEMORY_REGIONS = 1 report
"Warning; Cache is disabled (CACHE_SIZE = 0) and AUX interface is disabled (AUX_MEMORY_REGIONS = 0) but UC_MEMORY_REGIONS is greater than 1. Multiple UC_MEMORY_REGIONS are superflous in this configuration as all accesses will use the UC memory interface."
severity note;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
uc_select <= or_slv(umr_address_match);
c_select <= and_slv(not umr_address_match);
internal_oimm_readdata <= cacheint_oimm_readdata when cacheint_oimm_readdatavalid = '1' else
internal_uc_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid or internal_uc_oimm_readdatavalid;
end generate has_c_gen;
end generate has_uc_gen;
end generate no_aux_gen;
has_aux_gen : if AUX_MEMORY_REGIONS /= 0 generate
no_uc_gen : if UC_MEMORY_REGIONS = 0 generate
uc_select <= '0';
external_registers_idle <= aux_register_idle;
no_c_gen : if CACHE_SIZE = 0 generate
aux_select <= '1';
c_select <= '0';
internal_oimm_readdata <= internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= internal_aux_oimm_readdatavalid;
assert not ((unsigned(AMR0_ADDR_BASE) /= to_unsigned(0, AMR0_ADDR_BASE'length)) or
(signed(AMR0_ADDR_LAST) /= to_signed(-1, AMR0_ADDR_LAST'length))) report
"Warning; Cache is disabled (CACHE_SIZE = 0) and UC interface is disabled (UC_MEMORY_REGIONS = 0) but AMR0 address range does not encompass the full address range. All accesses will go to AUX interface, even those not in the AMR0 address range."
severity note;
assert AUX_MEMORY_REGIONS = 1 report
"Warning; Cache is disabled (CACHE_SIZE = 0) and UC interface is disabled (UC_MEMORY_REGIONS = 0) but AUX_MEMORY_REGIONS is greater than 1. Multiple AUX_MEMORY_REGIONS are superflous in this configuration as all accesses will use the AUX memory interface."
severity note;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
aux_select <= or_slv(amr_address_match);
c_select <= and_slv(not amr_address_match);
internal_oimm_readdata <= cacheint_oimm_readdata when cacheint_oimm_readdatavalid = '1' else
internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid or internal_aux_oimm_readdatavalid;
end generate has_c_gen;
end generate no_uc_gen;
has_uc_gen : if UC_MEMORY_REGIONS /= 0 generate
aux_select <= or_slv(amr_address_match);
external_registers_idle <= uc_register_idle and aux_register_idle;
no_c_gen : if CACHE_SIZE = 0 generate
uc_select <= and_slv(not amr_address_match);
c_select <= '0';
internal_oimm_readdata <= internal_uc_oimm_readdata when internal_uc_oimm_readdatavalid = '1' else
internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= internal_uc_oimm_readdatavalid or internal_aux_oimm_readdatavalid;
end generate no_c_gen;
has_c_gen : if CACHE_SIZE /= 0 generate
uc_select <= and_slv(not amr_address_match) and or_slv(umr_address_match);
c_select <= and_slv(not amr_address_match) and and_slv(not umr_address_match);
internal_oimm_readdata <= cacheint_oimm_readdata when cacheint_oimm_readdatavalid = '1' else
internal_uc_oimm_readdata when internal_uc_oimm_readdatavalid = '1' else
internal_aux_oimm_readdata;
internal_oimm_readdatavalid <= cacheint_oimm_readdatavalid or
internal_uc_oimm_readdatavalid or
internal_aux_oimm_readdatavalid;
end generate has_c_gen;
end generate has_uc_gen;
end generate has_aux_gen;
read_stall <=
((c_select and (c_max_outstanding_reads or (not uc_zero_outstanding_reads) or (not aux_zero_outstanding_reads))) or
(uc_select and (uc_max_outstanding_reads or (not c_zero_outstanding_reads) or (not aux_zero_outstanding_reads))) or
(aux_select and (aux_max_outstanding_reads or (not c_zero_outstanding_reads) or (not uc_zero_outstanding_reads))))
when MAX_OUTSTANDING_READS > 1 else
'0';
internal_oimm_waitrequest <= read_stall or
((cacheint_oimm_waitrequest and c_select) or
(internal_uc_oimm_waitrequest and uc_select) or
(internal_aux_oimm_waitrequest and aux_select));
cacheint_oimm_requestvalid <= internal_oimm_requestvalid and (not read_stall) and c_select;
cacheint_oimm_readnotwrite <= internal_oimm_readnotwrite;
internal_uc_oimm_requestvalid <= internal_oimm_requestvalid and (not read_stall) and uc_select;
internal_uc_oimm_readnotwrite <= internal_oimm_readnotwrite;
internal_aux_oimm_requestvalid <= internal_oimm_requestvalid and (not read_stall) and aux_select;
internal_aux_oimm_readnotwrite <= internal_oimm_readnotwrite;
--Note that we could include the updated read count when
--internal_oimm_readdatavalid is '1' but as long as more than one read is
--supported we can get full throughput with MAX_OUTSTANDING_READS-1 in
--flight.
c_zero_outstanding_reads <= '1' when c_outstanding_reads = to_unsigned(0, c_outstanding_reads'length) else '0';
c_max_outstanding_reads <=
'1' when c_outstanding_reads = to_unsigned(MAX_OUTSTANDING_READS, c_outstanding_reads'length) else '0';
uc_zero_outstanding_reads <= '1' when uc_outstanding_reads = to_unsigned(0, uc_outstanding_reads'length) else '0';
uc_max_outstanding_reads <=
'1' when uc_outstanding_reads = to_unsigned(MAX_OUTSTANDING_READS, uc_outstanding_reads'length) else '0';
aux_zero_outstanding_reads <= '1' when aux_outstanding_reads = to_unsigned(0, aux_outstanding_reads'length) else '0';
aux_max_outstanding_reads <=
'1' when aux_outstanding_reads = to_unsigned(MAX_OUTSTANDING_READS, aux_outstanding_reads'length) else '0';
process(clk)
begin
if rising_edge(clk) then
if internal_oimm_readdatavalid = '1' then
--Subtract one unless a new request has been issued
if (internal_oimm_requestvalid = '0' or
internal_oimm_readnotwrite = '0' or
internal_oimm_waitrequest = '1') then
if c_outstanding_reads /= to_unsigned(0, c_outstanding_reads'length) then
c_outstanding_reads <= c_outstanding_reads - to_unsigned(1, c_outstanding_reads'length);
end if;
if uc_outstanding_reads /= to_unsigned(0, uc_outstanding_reads'length) then
uc_outstanding_reads <= uc_outstanding_reads - to_unsigned(1, uc_outstanding_reads'length);
end if;
if aux_outstanding_reads /= to_unsigned(0, aux_outstanding_reads'length) then
aux_outstanding_reads <= aux_outstanding_reads - to_unsigned(1, aux_outstanding_reads'length);
end if;
end if;
else
if (internal_oimm_requestvalid = '1' and
internal_oimm_readnotwrite = '1' and
internal_oimm_waitrequest = '0') then
if c_select = '1' then
c_outstanding_reads <= c_outstanding_reads + to_unsigned(1, c_outstanding_reads'length);
end if;
if uc_select = '1' then
uc_outstanding_reads <= uc_outstanding_reads + to_unsigned(1, uc_outstanding_reads'length);
end if;
if aux_select = '1' then
aux_outstanding_reads <= aux_outstanding_reads + to_unsigned(1, aux_outstanding_reads'length);
end if;
end if;
end if;
if reset = '1' then
c_outstanding_reads <= to_unsigned(0, c_outstanding_reads'length);
uc_outstanding_reads <= to_unsigned(0, uc_outstanding_reads'length);
aux_outstanding_reads <= to_unsigned(0, aux_outstanding_reads'length);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Optional UC OIMM Register
-----------------------------------------------------------------------------
uc_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
REQUEST_REGISTER => UC_REQUEST_REGISTER,
RETURN_REGISTER => UC_RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => uc_register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => internal_uc_oimm_address,
slave_oimm_byteenable => internal_uc_oimm_byteenable,
slave_oimm_requestvalid => internal_uc_oimm_requestvalid,
slave_oimm_readnotwrite => internal_uc_oimm_readnotwrite,
slave_oimm_writedata => internal_uc_oimm_writedata,
slave_oimm_readdata => internal_uc_oimm_readdata,
slave_oimm_readdatavalid => internal_uc_oimm_readdatavalid,
slave_oimm_waitrequest => internal_uc_oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => uc_oimm_address,
master_oimm_byteenable => uc_oimm_byteenable,
master_oimm_requestvalid => uc_oimm_requestvalid,
master_oimm_readnotwrite => uc_oimm_readnotwrite,
master_oimm_writedata => uc_oimm_writedata,
master_oimm_readdata => uc_oimm_readdata,
master_oimm_readdatavalid => uc_oimm_readdatavalid,
master_oimm_waitrequest => uc_oimm_waitrequest
);
-----------------------------------------------------------------------------
-- Optional AUX OIMM Register
-----------------------------------------------------------------------------
aux_oimm_register : oimm_register
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH,
REQUEST_REGISTER => AUX_REQUEST_REGISTER,
RETURN_REGISTER => AUX_RETURN_REGISTER
)
port map (
clk => clk,
reset => reset,
register_idle => aux_register_idle,
--ORCA-internal memory-mapped slave
slave_oimm_address => internal_aux_oimm_address,
slave_oimm_byteenable => internal_aux_oimm_byteenable,
slave_oimm_requestvalid => internal_aux_oimm_requestvalid,
slave_oimm_readnotwrite => internal_aux_oimm_readnotwrite,
slave_oimm_writedata => internal_aux_oimm_writedata,
slave_oimm_readdata => internal_aux_oimm_readdata,
slave_oimm_readdatavalid => internal_aux_oimm_readdatavalid,
slave_oimm_waitrequest => internal_aux_oimm_waitrequest,
--ORCA-internal memory-mapped master
master_oimm_address => aux_oimm_address,
master_oimm_byteenable => aux_oimm_byteenable,
master_oimm_requestvalid => aux_oimm_requestvalid,
master_oimm_readnotwrite => aux_oimm_readnotwrite,
master_oimm_writedata => aux_oimm_writedata,
master_oimm_readdata => aux_oimm_readdata,
master_oimm_readdatavalid => aux_oimm_readdatavalid,
master_oimm_waitrequest => aux_oimm_waitrequest
);
end architecture;
| bsd-3-clause |
durai145/ace | demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| bsd-3-clause |
VectorBlox/risc-v | ip/idram/src/idram.vhd | 1 | 13579 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.idram_components.all;
use work.idram_utils.all;
entity idram is
generic (
--Port types: 0 -> AXI4Lite, 1 -> AXI3, 2 -> AXI4
INSTR_PORT_TYPE : natural range 0 to 2 := 0;
DATA_PORT_TYPE : natural range 0 to 2 := 0;
WRITE_FIRST_MODE : natural range 0 to 1 := 0;
SIZE : integer := 32768;
RAM_WIDTH : integer := 32;
ADDR_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
instr_AWID : in std_logic_vector(13 downto 0);
instr_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
instr_AWLEN : in std_logic_vector(7-(4*(INSTR_PORT_TYPE mod 2)) downto 0);
instr_AWSIZE : in std_logic_vector(2 downto 0);
instr_AWBURST : in std_logic_vector(1 downto 0);
instr_AWLOCK : in std_logic_vector(1 downto 0);
instr_AWCACHE : in std_logic_vector(3 downto 0);
instr_AWPROT : in std_logic_vector(2 downto 0);
instr_AWVALID : in std_logic;
instr_AWREADY : out std_logic;
instr_WID : in std_logic_vector(13 downto 0);
instr_WDATA : in std_logic_vector(RAM_WIDTH-1 downto 0);
instr_WSTRB : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
instr_WLAST : in std_logic;
instr_WVALID : in std_logic;
instr_WREADY : out std_logic;
instr_BID : out std_logic_vector(13 downto 0);
instr_BRESP : out std_logic_vector(1 downto 0);
instr_BVALID : out std_logic;
instr_BREADY : in std_logic;
instr_ARID : in std_logic_vector(13 downto 0);
instr_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
instr_ARLEN : in std_logic_vector(7-(4*(INSTR_PORT_TYPE mod 2)) downto 0);
instr_ARSIZE : in std_logic_vector(2 downto 0);
instr_ARBURST : in std_logic_vector(1 downto 0);
instr_ARLOCK : in std_logic_vector(1 downto 0);
instr_ARCACHE : in std_logic_vector(3 downto 0);
instr_ARPROT : in std_logic_vector(2 downto 0);
instr_ARVALID : in std_logic;
instr_ARREADY : out std_logic;
instr_RID : out std_logic_vector(13 downto 0);
instr_RDATA : out std_logic_vector(RAM_WIDTH-1 downto 0);
instr_RRESP : out std_logic_vector(1 downto 0);
instr_RLAST : out std_logic;
instr_RVALID : out std_logic;
instr_RREADY : in std_logic;
data_AWID : in std_logic_vector(13 downto 0);
data_AWADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_AWLEN : in std_logic_vector(7-(4*(DATA_PORT_TYPE mod 2)) downto 0);
data_AWSIZE : in std_logic_vector(2 downto 0);
data_AWBURST : in std_logic_vector(1 downto 0);
data_AWLOCK : in std_logic_vector(1 downto 0);
data_AWCACHE : in std_logic_vector(3 downto 0);
data_AWPROT : in std_logic_vector(2 downto 0);
data_AWVALID : in std_logic;
data_AWREADY : out std_logic;
data_WID : in std_logic_vector(13 downto 0);
data_WDATA : in std_logic_vector(RAM_WIDTH-1 downto 0);
data_WSTRB : in std_logic_vector((RAM_WIDTH/8)-1 downto 0);
data_WLAST : in std_logic;
data_WVALID : in std_logic;
data_WREADY : out std_logic;
data_BID : out std_logic_vector(13 downto 0);
data_BRESP : out std_logic_vector(1 downto 0);
data_BVALID : out std_logic;
data_BREADY : in std_logic;
data_ARID : in std_logic_vector(13 downto 0);
data_ARADDR : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_ARLEN : in std_logic_vector(7-(4*(DATA_PORT_TYPE mod 2)) downto 0);
data_ARSIZE : in std_logic_vector(2 downto 0);
data_ARBURST : in std_logic_vector(1 downto 0);
data_ARLOCK : in std_logic_vector(1 downto 0);
data_ARCACHE : in std_logic_vector(3 downto 0);
data_ARPROT : in std_logic_vector(2 downto 0);
data_ARVALID : in std_logic;
data_ARREADY : out std_logic;
data_RID : out std_logic_vector(13 downto 0);
data_RDATA : out std_logic_vector(RAM_WIDTH-1 downto 0);
data_RRESP : out std_logic_vector(1 downto 0);
data_RLAST : out std_logic;
data_RVALID : out std_logic;
data_RREADY : in std_logic
);
end entity idram;
architecture rtl of idram is
constant BYTES_PER_WORD : integer := RAM_WIDTH/8;
signal address : std_logic_vector(log2(SIZE/BYTES_PER_WORD)-1 downto 0);
signal write_en : std_logic;
signal instr_AWVALID_latched : std_logic;
signal instr_AWADDR_latched : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal instr_WVALID_latched : std_logic;
signal instr_WDATA_latched : std_logic_vector(RAM_WIDTH-1 downto 0);
signal instr_WSTRB_latched : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal instr_AWREADY_internal : std_logic;
signal instr_WREADY_internal : std_logic;
signal instr_BVALID_internal : std_logic;
signal instr_ARREADY_internal : std_logic;
signal instr_RVALID_internal : std_logic;
signal instr_address : std_logic_vector(log2(SIZE/BYTES_PER_WORD)-1 downto 0);
signal instr_read_en : std_logic;
signal instr_write_en : std_logic;
signal instr_write_data : std_logic_vector(RAM_WIDTH-1 downto 0);
signal instr_byte_sel : std_logic_vector(RAM_WIDTH/8-1 downto 0);
signal instr_en : std_logic;
signal instr_read_resp_stalled : std_logic;
signal instr_write_resp_stalled : std_logic;
signal data_AWVALID_latched : std_logic;
signal data_AWADDR_latched : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal data_WVALID_latched : std_logic;
signal data_WDATA_latched : std_logic_vector(RAM_WIDTH-1 downto 0);
signal data_WSTRB_latched : std_logic_vector((RAM_WIDTH/8)-1 downto 0);
signal data_AWREADY_internal : std_logic;
signal data_WREADY_internal : std_logic;
signal data_BVALID_internal : std_logic;
signal data_ARREADY_internal : std_logic;
signal data_RVALID_internal : std_logic;
signal data_address : std_logic_vector(log2(SIZE/BYTES_PER_WORD)-1 downto 0);
signal data_read_en : std_logic;
signal data_write_en : std_logic;
signal data_write_data : std_logic_vector(RAM_WIDTH-1 downto 0);
signal data_byte_sel : std_logic_vector(RAM_WIDTH/8-1 downto 0);
signal data_en : std_logic;
signal data_read_resp_stalled : std_logic;
signal data_write_resp_stalled : std_logic;
begin
instr_RRESP <= (others => '0');
instr_BRESP <= (others => '0');
instr_ARREADY_internal <= (not reset) and
(not instr_read_resp_stalled) and
(not instr_AWVALID_latched) and
(not instr_WVALID_latched);
instr_ARREADY <= instr_ARREADY_internal;
instr_AWREADY_internal <= (not reset) and
(not instr_write_resp_stalled) and
(not instr_AWVALID_latched);
instr_AWREADY <= instr_AWREADY_internal;
instr_WREADY_internal <= instr_AWREADY_internal;
instr_WREADY <= (not reset) and
(not instr_write_resp_stalled) and
(not instr_WVALID_latched);
instr_address <=
instr_ARADDR(instr_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when
instr_read_en = '1' else
instr_AWADDR(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when instr_AWVALID_latched = '0' else
instr_AWADDR_latched(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD));
instr_read_en <= instr_ARVALID and instr_ARREADY_internal;
instr_write_en <= ((instr_AWVALID and instr_AWREADY_internal) or instr_AWVALID_latched) and
((instr_WVALID and instr_WREADY_internal) or instr_WVALID_latched);
instr_write_data <= instr_WDATA when instr_WVALID_latched = '0' else
instr_WDATA_latched;
instr_byte_sel <= (others => '1') when instr_read_en = '1' else
instr_WSTRB when instr_WVALID_latched = '0' else
instr_WSTRB_latched;
instr_en <= instr_write_en or instr_read_en;
instr_read_resp_stalled <= instr_RVALID_internal and (not instr_RREADY);
instr_RVALID <= instr_RVALID_internal;
instr_write_resp_stalled <= instr_BVALID_internal and (not instr_BREADY);
instr_BVALID <= instr_BVALID_internal;
data_RRESP <= (others => '0');
data_BRESP <= (others => '0');
data_ARREADY_internal <= (not reset) and
(not data_read_resp_stalled) and
(not data_AWVALID_latched) and
(not data_WVALID_latched);
data_ARREADY <= data_ARREADY_internal;
data_AWREADY_internal <= (not reset) and
(not data_write_resp_stalled) and
(not data_AWVALID_latched);
data_AWREADY <= data_AWREADY_internal;
data_WREADY_internal <= data_AWREADY_internal;
data_WREADY <= (not reset) and
(not data_write_resp_stalled) and
(not data_WVALID_latched);
data_address <=
data_ARADDR(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when
data_read_en = '1' else
data_AWADDR(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD)) when data_AWVALID_latched = '0' else
data_AWADDR_latched(data_address'left+log2(BYTES_PER_WORD) downto log2(BYTES_PER_WORD));
data_read_en <= data_ARVALID and data_ARREADY_internal;
data_write_en <= ((data_AWVALID and data_AWREADY_internal) or data_AWVALID_latched) and
((data_WVALID and data_WREADY_internal) or data_WVALID_latched);
data_write_data <= data_WDATA when data_WVALID_latched = '0' else
data_WDATA_latched;
data_byte_sel <= (others => '1') when data_read_en = '1' else
data_WSTRB when data_WVALID_latched = '0' else
data_WSTRB_latched;
data_en <= data_write_en or data_read_en;
data_read_resp_stalled <= data_RVALID_internal and (not data_RREADY);
data_RVALID <= data_RVALID_internal;
data_write_resp_stalled <= data_BVALID_internal and (not data_BREADY);
data_BVALID <= data_BVALID_internal;
instr_port : process(clk)
begin
if rising_edge(clk) then
if instr_AWVALID = '1' and instr_AWREADY_internal = '1' then
instr_AWVALID_latched <= '1';
instr_AWADDR_latched <= instr_AWADDR;
end if;
if instr_WVALID = '1' and instr_WREADY_internal = '1' then
instr_WVALID_latched <= '1';
instr_WDATA_latched <= instr_WDATA;
instr_WSTRB_latched <= instr_WSTRB;
end if;
if instr_write_en = '1' then
instr_AWVALID_latched <= '0';
instr_WVALID_latched <= '0';
end if;
if instr_RREADY = '1' then
instr_RVALID_internal <= '0';
end if;
if instr_read_en = '1' then
instr_RVALID_internal <= '1';
instr_RID <= instr_ARID;
end if;
if instr_BREADY = '1' then
instr_BVALID_internal <= '0';
end if;
if instr_write_en = '1' then
instr_BVALID_internal <= '1';
instr_BID <= instr_AWID;
end if;
if reset = '1' then
instr_AWVALID_latched <= '0';
instr_WVALID_latched <= '0';
instr_RVALID_internal <= '0';
instr_BVALID_internal <= '0';
end if;
end if;
end process;
data_port : process(clk)
begin
if rising_edge(clk) then
if data_AWVALID = '1' and data_AWREADY_internal = '1' then
data_AWVALID_latched <= '1';
data_AWADDR_latched <= data_AWADDR;
end if;
if data_WVALID = '1' and data_WREADY_internal = '1' then
data_WVALID_latched <= '1';
data_WDATA_latched <= data_WDATA;
data_WSTRB_latched <= data_WSTRB;
end if;
if data_write_en = '1' then
data_AWVALID_latched <= '0';
data_WVALID_latched <= '0';
end if;
if data_RREADY = '1' then
data_RVALID_internal <= '0';
end if;
if data_read_en = '1' then
data_RVALID_internal <= '1';
data_RID <= data_ARID;
end if;
if data_BREADY = '1' then
data_BVALID_internal <= '0';
end if;
if data_write_en = '1' then
data_BVALID_internal <= '1';
data_BID <= data_AWID;
end if;
if reset = '1' then
data_AWVALID_latched <= '0';
data_WVALID_latched <= '0';
data_RVALID_internal <= '0';
data_BVALID_internal <= '0';
end if;
end if;
end process;
ram : component idram_behav
generic map (
RAM_DEPTH => SIZE/4,
RAM_WIDTH => RAM_WIDTH,
WRITE_FIRST => (WRITE_FIRST_MODE /= 0)
)
port map (
clk => clk,
instr_address => instr_address,
instr_data_in => instr_write_data,
instr_we => instr_write_en,
instr_en => instr_en,
instr_be => instr_byte_sel,
instr_readdata => instr_RDATA,
data_address => data_address,
data_data_in => data_write_data,
data_we => data_write_en,
data_en => data_en,
data_be => data_byte_sel,
data_readdata => data_RDATA
);
--Only valid for A4L, needs fixing for AXI3/AXI4
instr_RLAST <= '1';
data_RLAST <= '1';
end architecture rtl;
| bsd-3-clause |
VectorBlox/risc-v | ip/orca/hdl/oimm_register.vhd | 1 | 12133 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
entity oimm_register is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
LOG2_BURSTLENGTH : positive := 2;
REQUEST_REGISTER : request_register_type;
RETURN_REGISTER : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
register_idle : out std_logic;
--ORCA-internal memory-mapped slave
slave_oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
slave_oimm_burstlength : in std_logic_vector(LOG2_BURSTLENGTH downto 0) := (0 => '1', others => '0');
slave_oimm_burstlength_minus1 : in std_logic_vector(LOG2_BURSTLENGTH-1 downto 0) := (others => '0');
slave_oimm_byteenable : in std_logic_vector((DATA_WIDTH/8)-1 downto 0);
slave_oimm_requestvalid : in std_logic;
slave_oimm_readnotwrite : in std_logic;
slave_oimm_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0);
slave_oimm_writelast : in std_logic := '1';
slave_oimm_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
slave_oimm_readdatavalid : out std_logic;
slave_oimm_waitrequest : out std_logic;
--ORCA-internal memory-mapped master
master_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
master_oimm_burstlength : out std_logic_vector(LOG2_BURSTLENGTH downto 0);
master_oimm_burstlength_minus1 : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
master_oimm_byteenable : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
master_oimm_requestvalid : out std_logic;
master_oimm_readnotwrite : out std_logic;
master_oimm_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0);
master_oimm_writelast : out std_logic;
master_oimm_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
master_oimm_readdatavalid : in std_logic;
master_oimm_waitrequest : in std_logic
);
end entity oimm_register;
architecture rtl of oimm_register is
signal slave_oimm_waitrequest_signal : std_logic;
signal master_oimm_requestvalid_signal : std_logic;
begin
slave_oimm_waitrequest <= slave_oimm_waitrequest_signal;
master_oimm_requestvalid <= master_oimm_requestvalid_signal;
-----------------------------------------------------------------------------
-- Optional Memory Request Register
-----------------------------------------------------------------------------
--Passthrough, lowest fmax but no extra resources or added latency.
no_request_register_gen : if REQUEST_REGISTER = OFF generate
master_oimm_address <= slave_oimm_address;
master_oimm_burstlength <= slave_oimm_burstlength;
master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1;
master_oimm_byteenable <= slave_oimm_byteenable;
master_oimm_requestvalid_signal <= slave_oimm_requestvalid;
master_oimm_readnotwrite <= slave_oimm_readnotwrite;
master_oimm_writedata <= slave_oimm_writedata;
master_oimm_writelast <= slave_oimm_writelast;
slave_oimm_waitrequest_signal <= master_oimm_waitrequest;
register_idle <= '1'; --idle is state-only
end generate no_request_register_gen;
--Light register; breaks waitrequest/stall combinational path but does not break
--address/etc. path. Does not add latency if slave is not asserting
--waitrequest, but will reduce throughput if the slave does.
light_request_register_gen : if REQUEST_REGISTER = LIGHT generate
signal slave_oimm_address_held : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal slave_oimm_burstlength_held : std_logic_vector(LOG2_BURSTLENGTH downto 0);
signal slave_oimm_burstlength_minus1_held : std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
signal slave_oimm_byteenable_held : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal slave_oimm_requestvalid_held : std_logic;
signal slave_oimm_readnotwrite_held : std_logic;
signal slave_oimm_writedata_held : std_logic_vector(DATA_WIDTH-1 downto 0);
signal slave_oimm_writelast_held : std_logic;
begin
master_oimm_address <= slave_oimm_address_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_address;
master_oimm_burstlength <= slave_oimm_burstlength_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_burstlength;
master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_burstlength_minus1;
master_oimm_byteenable <= slave_oimm_byteenable_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_byteenable;
master_oimm_requestvalid_signal <= slave_oimm_requestvalid_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_requestvalid;
master_oimm_readnotwrite <= slave_oimm_readnotwrite_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_readnotwrite;
master_oimm_writedata <= slave_oimm_writedata_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_writedata;
master_oimm_writelast <= slave_oimm_writelast_held when slave_oimm_waitrequest_signal = '1' else slave_oimm_writelast;
process(clk)
begin
if rising_edge(clk) then
--When coming out of reset, need to put waitrequest down
if slave_oimm_requestvalid_held = '0' then
slave_oimm_waitrequest_signal <= '0';
end if;
if master_oimm_waitrequest = '0' then
slave_oimm_waitrequest_signal <= '0';
end if;
if slave_oimm_waitrequest_signal = '0' then
slave_oimm_address_held <= slave_oimm_address;
slave_oimm_burstlength_held <= slave_oimm_burstlength;
slave_oimm_burstlength_minus1_held <= slave_oimm_burstlength_minus1;
slave_oimm_byteenable_held <= slave_oimm_byteenable;
slave_oimm_requestvalid_held <= slave_oimm_requestvalid;
slave_oimm_readnotwrite_held <= slave_oimm_readnotwrite;
slave_oimm_writedata_held <= slave_oimm_writedata;
slave_oimm_writelast_held <= slave_oimm_writelast;
slave_oimm_waitrequest_signal <= master_oimm_waitrequest and slave_oimm_requestvalid;
end if;
if reset = '1' then
slave_oimm_requestvalid_held <= '0';
slave_oimm_waitrequest_signal <= '1';
end if;
end if;
end process;
register_idle <= not slave_oimm_waitrequest_signal; --idle is state-only
end generate light_request_register_gen;
--Full register; breaks waitrequest/stall combinational path and address/etc.
--path. Always adds one cycle of latency but does not reduce throughput.
full_request_register_gen : if REQUEST_REGISTER = FULL generate
signal registered_oimm_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal registered_oimm_burstlength : std_logic_vector(LOG2_BURSTLENGTH downto 0);
signal registered_oimm_burstlength_minus1 : std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
signal registered_oimm_byteenable : std_logic_vector((DATA_WIDTH/8)-1 downto 0);
signal registered_oimm_requestvalid : std_logic;
signal registered_oimm_readnotwrite : std_logic;
signal registered_oimm_writedata : std_logic_vector(DATA_WIDTH-1 downto 0);
signal registered_oimm_writelast : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
--When coming out of reset, need to put waitrequest down
if registered_oimm_requestvalid = '0' then
slave_oimm_waitrequest_signal <= '0';
end if;
if master_oimm_waitrequest = '0' then
master_oimm_requestvalid_signal <= '0';
if registered_oimm_requestvalid = '1' then
master_oimm_address <= registered_oimm_address;
master_oimm_burstlength <= registered_oimm_burstlength;
master_oimm_burstlength_minus1 <= registered_oimm_burstlength_minus1;
master_oimm_byteenable <= registered_oimm_byteenable;
master_oimm_readnotwrite <= registered_oimm_readnotwrite;
master_oimm_requestvalid_signal <= registered_oimm_requestvalid;
master_oimm_writedata <= registered_oimm_writedata;
master_oimm_writelast <= registered_oimm_writelast;
registered_oimm_requestvalid <= '0';
slave_oimm_waitrequest_signal <= '0';
else
master_oimm_address <= slave_oimm_address;
master_oimm_burstlength <= slave_oimm_burstlength;
master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1;
master_oimm_byteenable <= slave_oimm_byteenable;
master_oimm_readnotwrite <= slave_oimm_readnotwrite;
master_oimm_requestvalid_signal <= slave_oimm_requestvalid and (not slave_oimm_waitrequest_signal);
master_oimm_writedata <= slave_oimm_writedata;
master_oimm_writelast <= slave_oimm_writelast;
end if;
else
if slave_oimm_waitrequest_signal = '0' then
if master_oimm_requestvalid_signal = '1' then
registered_oimm_address <= slave_oimm_address;
registered_oimm_burstlength <= slave_oimm_burstlength;
registered_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1;
registered_oimm_byteenable <= slave_oimm_byteenable;
registered_oimm_requestvalid <= slave_oimm_requestvalid;
registered_oimm_readnotwrite <= slave_oimm_readnotwrite;
registered_oimm_writedata <= slave_oimm_writedata;
registered_oimm_writelast <= slave_oimm_writelast;
slave_oimm_waitrequest_signal <= slave_oimm_requestvalid;
else
master_oimm_address <= slave_oimm_address;
master_oimm_burstlength <= slave_oimm_burstlength;
master_oimm_burstlength_minus1 <= slave_oimm_burstlength_minus1;
master_oimm_byteenable <= slave_oimm_byteenable;
master_oimm_readnotwrite <= slave_oimm_readnotwrite;
master_oimm_requestvalid_signal <= slave_oimm_requestvalid;
master_oimm_writedata <= slave_oimm_writedata;
master_oimm_writelast <= slave_oimm_writelast;
end if;
end if;
end if;
if reset = '1' then
master_oimm_requestvalid_signal <= '0';
registered_oimm_requestvalid <= '0';
slave_oimm_waitrequest_signal <= '1';
end if;
end if;
end process;
register_idle <= not master_oimm_requestvalid_signal; --idle is state-only
end generate full_request_register_gen;
-----------------------------------------------------------------------------
-- Optional Data Memory Return Register
-----------------------------------------------------------------------------
no_return_register_gen : if not RETURN_REGISTER generate
slave_oimm_readdata <= master_oimm_readdata;
slave_oimm_readdatavalid <= master_oimm_readdatavalid;
end generate no_return_register_gen;
return_register_gen : if RETURN_REGISTER generate
process(clk)
begin
if rising_edge(clk) then
slave_oimm_readdata <= master_oimm_readdata;
slave_oimm_readdatavalid <= master_oimm_readdatavalid;
end if;
end process;
end generate return_register_gen;
end architecture rtl;
| bsd-3-clause |
VectorBlox/risc-v | ip/edge_extender/src/edge_extender.vhd | 1 | 1100 | library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity edge_extender is
generic (
NUM_CYCLES : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
interrupt_in : in std_logic;
interrupt_out : out std_logic
);
end entity edge_extender;
architecture rtl of edge_extender is
signal register_bank : std_logic_vector(NUM_CYCLES-1 downto 0);
begin
gen_reg_bank :
for i in 1 to NUM_CYCLES-1 generate
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
register_bank(i) <= '0';
else
register_bank(i) <= register_bank(i-1);
end if;
end if;
end process;
end generate gen_reg_bank;
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
register_bank(0) <= '0';
else
register_bank(0) <= interrupt_in;
end if;
end if;
end process;
interrupt_out <= '1' when register_bank /= std_logic_vector(to_unsigned(0, NUM_CYCLES))
else '0';
end architecture rtl;
| bsd-3-clause |
alvieboy/xtc-base | dcache2.vhd | 1 | 23045 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synopsys translate_off
use work.txt_util.all;
-- synopsys translate_on
entity dcache is
generic (
ADDRESS_HIGH: integer := 31;
CACHE_MAX_BITS: integer := 11; -- 8 Kb
CACHE_LINE_SIZE_BITS: integer := 6 -- 64 bytes
);
port (
syscon: in wb_syscon_type;
ci: in dcache_in_type;
co: out dcache_out_type;
mwbi: in wb_miso_type;
mwbo: out wb_mosi_type
);
end dcache;
architecture behave of dcache is
constant CACHE_LINE_ID_BITS: integer := CACHE_MAX_BITS-CACHE_LINE_SIZE_BITS;
subtype address_type is std_logic_vector(ADDRESS_HIGH downto 2);
-- A line descriptor
subtype line_number_type is std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
-- Offset within a line
subtype line_offset_type is std_logic_vector(CACHE_LINE_SIZE_BITS-1-2 downto 0);
-- A tag descriptor
subtype tag_type is std_logic_vector((ADDRESS_HIGH-CACHE_MAX_BITS) downto 0);
-- A full tag memory descriptor. Includes valid bit and dirty bit
subtype full_tag_type is std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+2 downto 0);
constant VALIDBIT: integer := ADDRESS_HIGH-CACHE_MAX_BITS+1;
constant DIRTYBIT: integer := ADDRESS_HIGH-CACHE_MAX_BITS+2;
------------------------------------------------------------------------------
type state_type is (
idle,
readline,
preparewb,
writeback,
recover,
write_after_fill,
settle,
flush,
directmemory
);
constant BURSTWORDS: integer := (2**(CACHE_LINE_SIZE_BITS-2))-1;
type regs_type is record
req: std_logic;
req_addr: address_type;
req_we: std_logic;
req_wmask: std_logic_vector(3 downto 0);
req_data: std_logic_vector(31 downto 0);
req_tag: std_logic_vector(31 downto 0);
req_accesstype: std_logic_vector(1 downto 0);
fill_offset_r: line_offset_type;
req_offset: line_offset_type;
fill_offset_w: line_offset_type;
finished_w: line_offset_type;
fill_tag: tag_type;
fill_line_number: line_number_type;
flush_line_number: line_number_type;
fill_r_done: std_logic;
ack_write: std_logic;
writeback_tag: tag_type;
state: state_type;
misses: integer;
rvalid: std_logic;
wr_conflict: std_logic;
ack_q: std_logic;
ack_q_q: std_logic;
flush_req: std_logic;
in_flush: std_logic;
count: integer range 0 to BURSTWORDS;
end record;
function address_to_tag(a: in address_type) return tag_type is
variable t: tag_type;
begin
t:= a(ADDRESS_HIGH downto CACHE_MAX_BITS);
return t;
end address_to_tag;
function address_to_line_number(a: in address_type) return line_number_type is
variable r: line_number_type;
begin
r:=a(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
return r;
end address_to_line_number;
function address_to_line_offset(a: in address_type) return line_offset_type is
variable r: line_offset_type;
begin
r:=a(CACHE_LINE_SIZE_BITS-1 downto 2);
return r;
end address_to_line_offset;
------------------------------------------------------------------------------
-- extracted values from port A
signal line_number: line_number_type;
-- Some helpers
signal hit: std_logic;
--signal miss: std_logic;
--attribute keep : string;
-- attribute keep of a_miss : signal is "true";
--attribute keep of b_miss : signal is "true";
--signal a_b_conflict: std_logic;
-- Connection to tag memory
signal tmem_ena: std_logic;
signal tmem_wea: std_logic;
signal tmem_addra: line_number_type;
signal tmem_dia: full_tag_type;
signal tmem_doa: full_tag_type;
signal tmem_enb: std_logic;
signal tmem_web: std_logic;
signal tmem_addrb: line_number_type;
signal tmem_dib: full_tag_type;
signal tmem_dob: full_tag_type;
signal cmem_ena: std_logic;
signal cmem_wea: std_logic_vector(3 downto 0);
signal cmem_dia: std_logic_vector(31 downto 0);
signal cmem_doa: std_logic_vector(31 downto 0);
signal cmem_addra: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal cmem_enb: std_logic;
signal cmem_web: std_logic_vector(3 downto 0);
signal cmem_dib: std_logic_vector(31 downto 0);
signal cmem_dob: std_logic_vector(31 downto 0);
signal cmem_addrb: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal r: regs_type;
signal same_address: std_logic;
constant offset_all_ones: line_offset_type := (others => '1');
constant offset_all_zeroes: line_offset_type := (others => '0');
constant line_number_all_ones: line_number_type := (others => '1');
signal dbg_valid: std_logic;
signal dbg_dirty: std_logic;
signal dbg_miss: std_logic;
signal dbg_tag_address: tag_type;
signal dbg_tag_stored: tag_type;
signal req_in_progess: std_logic;
signal req_last: std_logic;
signal wb_stb, wb_cyc: std_logic;
begin
-- These are alias, but written as signals so we can inspect them
line_number <= address_to_line_number(ci.address(address_type'RANGE));
-- TAG memory
tagmem: entity work.generic_dp_ram_rf
generic map (
address_bits => CACHE_LINE_ID_BITS,
data_bits => ADDRESS_HIGH-CACHE_MAX_BITS+3
)
port map (
clka => syscon.clk,
ena => tmem_ena,
wea => tmem_wea,
addra => tmem_addra,
dia => tmem_dia,
doa => tmem_doa,
clkb => syscon.clk,
enb => tmem_enb,
web => tmem_web,
addrb => tmem_addrb,
dib => tmem_dib,
dob => tmem_dob
);
-- Cache memory
memgen: for i in 0 to 3 generate
cachemem: entity work.generic_dp_ram_rf
generic map (
address_bits => cmem_addra'LENGTH,
data_bits => 8
)
port map (
clka => syscon.clk,
ena => cmem_ena,
wea => cmem_wea(i),
addra => cmem_addra,
dia => cmem_dia(((i+1)*8)-1 downto i*8),
doa => cmem_doa(((i+1)*8)-1 downto i*8),
clkb => syscon.clk,
enb => cmem_enb,
web => cmem_web(i),
addrb => cmem_addrb,
dib => cmem_dib(((i+1)*8)-1 downto i*8),
dob => cmem_dob(((i+1)*8)-1 downto i*8)
);
end generate;
co.in_flush <= r.in_flush;
reqcnt_inst: entity work.reqcnt
port map (
clk => syscon.clk,
rst => syscon.rst,
stb => wb_stb,
cyc => wb_cyc,
stall => mwbi.stall,
ack => mwbi.ack,
req => req_in_progess,
lastreq => req_last,
count => open
);
mwbo.cyc<=wb_cyc;
mwbo.stb<=wb_stb;
process(r,syscon.clk,syscon.rst, ci, mwbi, tmem_doa,
tmem_doa, tmem_dob, line_number, cmem_doa, cmem_dob,req_last)
variable w: regs_type;
variable have_request: std_logic;
variable will_busy: std_logic;
variable valid: std_logic;
--variable stall: std_logic;
variable miss: std_logic;
begin
w := r;
valid :='0';
--stall:='0';
miss := DontCareValue;
will_busy := '0';
co.valid<='0';
co.stall<='0';
wb_cyc <= '0';
wb_stb <= DontCareValue;
mwbo.adr <= (others => DontCareValue);
mwbo.dat <= (others => DontCareValue);
mwbo.tag <= (others => DontCareValue);
mwbo.we <= DontCareValue;
mwbo.sel<=(others => '1');
tmem_addra <= line_number;
tmem_addrb <= address_to_line_number( r.req_addr );--(others => DontCareValue);
tmem_ena <= '1';
tmem_wea <= '0';
tmem_enb <= '0';
--tmem_web <= '0';
--tmem_dib(tag_type'RANGE) <= address_to_tag(ci.address(r.req_addr'RANGE));--(others => DontCareValue);
tmem_dib(tag_type'RANGE) <= address_to_tag(r.req_addr);--(others => DontCareValue);
tmem_dib(DIRTYBIT)<=DontCareValue;
tmem_dib(VALIDBIT)<=DontCareValue;
tmem_dia <= (others => DontCareValue);
-- content memory is accessed at same time as tag memory
cmem_addra <= ci.address(CACHE_MAX_BITS-1 downto 2);
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);
cmem_ena <= ci.enable and ci.strobe;
if ci.we='0' then
cmem_wea <= "0000";
else
if ci.accesstype/=ACCESS_NOCACHE then
cmem_wea <= ci.wmask;
else
cmem_wea <= "0000";
end if;
end if;
cmem_web <= "0000";
cmem_dia <= ci.data;
cmem_enb <= r.req;-- and not miss; --ci.b_enable;
--cmem_dia <= (others => DontCareValue); -- No writes on port A
cmem_dib <= r.req_data;--ci.b_data_in;--(others => DontCareValue);
co.data <= cmem_doa;
--co.b_data_out <= cmem_dob;
--w.ack_b_write := '0';
w.rvalid := 'X';
-- synopsys translate_off
dbg_valid <= tmem_doa(VALIDBIT);
dbg_dirty <= tmem_doa(DIRTYBIT);
-- synopsys translate_on
tmem_web <= '0';
co.tag <= r.req_tag;
w.ack_q_q := '0';
w.ack_q := '0';
-- synopsys translate_off
dbg_tag_address<=address_to_tag(r.req_addr);
dbg_tag_stored<=tmem_doa(tag_type'RANGE);
-- synopsys translate_on
case r.state is
when idle =>
co.stall<='0';
-- Now, after reading from tag memory....
if (r.req='1') then
-- We had a request, check
miss:='1';
if tmem_doa(VALIDBIT)='1' then
if tmem_doa(tag_type'RANGE) = address_to_tag(r.req_addr) then
miss:='0';
end if;
end if;
-- For noncache access, we mark it as
-- miss.
if r.req_accesstype=ACCESS_NOCACHE then
miss := '1';
end if;
co.valid<=not miss;
else
co.valid<='0';
miss:='0';
end if;
-- Miss handling
if miss='1' then
-- Invalidate any potential write in cachemem from
-- a netx request.
--cmem_wea<="0000";
cmem_ena<='0';
if r.req_accesstype/=ACCESS_NOCACHE then
co.stall <= '1';
valid := '0';
w.misses := r.misses+1;
w.fill_tag := address_to_tag(r.req_addr);
w.fill_line_number := address_to_line_number(r.req_addr);
w.count := BURSTWORDS;
w.fill_r_done := '0';
w.fill_offset_r := r.req_offset;
w.fill_offset_w := r.req_offset;
if tmem_doa(VALIDBIT)='1' then
if tmem_doa(DIRTYBIT)='1' then
-- Read/Write miss to a dirty line for a different
-- tag.
w.writeback_tag := tmem_doa(tag_type'RANGE);
-- TODO: if this is a direct access, no need to writeback.
w.rvalid := '0';
--w.fill_r_done := '0';
w.fill_offset_r := (others => '0');
w.fill_offset_w := (others => '0');
if r.req_we='1' then
--- Oops, we wrote to the wrong line.
w.state := recover; -- was writeback
else
w.state := preparewb;
end if;
will_busy :='1';
else
-- Read/Write to a non-dirty line for a different
-- tag.
w.state := readline;
will_busy :='1';
end if;
else
-- Read/Write to a non-present line for a different
-- tag.
if r.req_we='1' then
-- It's a write.
case r.req_accesstype is
when ACCESS_WB_WA =>
w.state := readline;
when ACCESS_WB_NA | ACCESS_WT =>
-- Non-cacheable access, no allocate or writethrough.
-- Need to perform write directly to memory
w.state := directmemory;
w.fill_r_done := '0';
when others =>
--
end case;
else
-- It's a read.
w.state := readline;
end if;
will_busy :='1';
end if;
else
-- Non-cacheable address.
w.state := directmemory;
w.fill_r_done := '0';
will_busy := '1';
co.stall<='1';
end if;
else
-- This is a hit. Make sure we write the dirty bit (for writes).
tmem_web<=r.req_we;
tmem_enb<=r.req;
tmem_dib(DIRTYBIT)<='1';
tmem_dib(VALIDBIT)<='1';
valid := '1';
end if;
if r.flush_req='1' then
will_busy :='1';
co.stall <= '1';
cmem_enb <= '0';
cmem_dib <= (others => DontCareValue);
cmem_addrb <= (others => DontCareValue);
w.state := flush;
w.fill_line_number := (others => '0');
w.flush_line_number := (others => '0');
end if;
have_request := '0';
-- Queue requests
if will_busy='0' then
w.req := ci.strobe and ci.enable;
w.req_we := ci.we;
w.req_wmask := ci.wmask;
w.req_data := ci.data;
w.req_tag := ci.tag;
w.req_accesstype := ci.accesstype;
co.stall<='0';
if ci.strobe='1' and ci.enable='1' then
have_request := '1';
w.req_addr(address_type'RANGE) := ci.address(address_type'RANGE);
w.req_offset := address_to_line_offset(ci.address(address_type'RANGE));
end if;
end if;
when directmemory =>
co.stall <= '1';
tmem_web <= '0';
mwbo.adr <=(others => '0');
mwbo.adr (ADDRESS_HIGH downto 2) <= r.req_addr;
wb_cyc <='1';
wb_stb <=not r.fill_r_done;
mwbo.we <= r.req_we;
mwbo.sel <= r.req_wmask;
mwbo.dat <= r.req_data;
mwbo.tag <= r.req_tag;
co.data <= mwbi.dat;
co.tag <= mwbi.tag;
if mwbi.stall='0' then
w.fill_r_done:='1';
end if;
if mwbi.ack='1' then
co.valid<='1';
co.stall<='0';
w.req := ci.strobe and ci.enable;
w.req_we := ci.we;
w.req_wmask := ci.wmask;
w.req_data := ci.data;
w.req_tag := ci.tag;
w.req_accesstype := ci.accesstype;
co.stall<='0';
if ci.strobe='1' and ci.enable='1' then
have_request := '1';
w.req_addr(address_type'RANGE) := ci.address(address_type'RANGE);
w.req_offset := address_to_line_offset(ci.address(address_type'RANGE));
end if;
w.state:=idle;
end if;
when readline =>
co.stall <= '1';
tmem_web <= '0';
w.ack_q := mwbi.ack;
w.ack_q_q := r.ack_q;
mwbo.adr<=(others => '0');
mwbo.adr(ADDRESS_HIGH downto 2) <= r.fill_tag & r.fill_line_number & r.fill_offset_r;
mwbo.tag(cmem_addrb'LENGTH-1 downto 0) <= r.fill_line_number & r.fill_offset_r;
mwbo.tag(cmem_addrb'LENGTH) <= '1';
wb_cyc<='1';
wb_stb<=not r.fill_r_done;
mwbo.we<='0';
cmem_addrb <= mwbi.tag(cmem_addrb'LENGTH-1 downto 0);--r.fill_line_number & r.fill_offset_w;
cmem_addra <= r.req_addr(CACHE_MAX_BITS-1 downto 2);--r.req_offset;--(others => DontCareValue);
--cmem_enb <= '1';
cmem_enb <= mwbi.tag(cmem_addrb'LENGTH);-- <= '1';
cmem_ena <= '1';
cmem_wea <= (others => '0');
cmem_dia <= (others => 'X');
cmem_web <= (others => mwbi.ack);
cmem_dib <= mwbi.dat;
if mwbi.stall='0' and r.fill_r_done='0' then
if w.count=0 then--r.fill_offset_r = offset_all_ones then
w.fill_r_done := '1';
else
w.fill_offset_r := std_logic_vector(unsigned(r.fill_offset_r) + 1);
w.count := w.count - 1;
end if;
end if;
--if r.ack_q='1' then
--end if;
if mwbi.ack='1' then
w.fill_offset_w := std_logic_vector(unsigned(r.fill_offset_w) + 1);
w.finished_w := r.fill_offset_w;
--if r.fill_offset_w=offset_all_ones then
if r.fill_r_done='1' and req_last='1' then
w.state := settle;
tmem_addrb <= r.fill_line_number;
tmem_dib(tag_type'RANGE) <= r.fill_tag;
tmem_dib(VALIDBIT)<='1';
tmem_dib(DIRTYBIT)<=r.req_we;
tmem_web<='1';
tmem_enb<='1';
tmem_ena<='0';
if r.req_we='1' then
-- Perform write
w.state := write_after_fill;
end if;
end if;
else
cmem_dia <= (others => DontCareValue);
cmem_dib <= (others => DontCareValue);
end if;
-- Validate read for IWF
if true then
if r.ack_q_q='1' then
if r.finished_w=r.req_offset then
co.valid<='1';
co.tag<=r.req_tag;
w.req :='0';
end if;
end if;
end if;
when recover =>
-- Recover lost data on the content memory
co.stall <= '1';
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);
cmem_enb <= '1';
cmem_web <= "1111";
cmem_dib <= cmem_doa;
cmem_wea<="0000"; -- Don't allow writes.
-- synthesis translate_off
--report "Recover write";
-- synthesis translate_on
w.rvalid := '0';
w.fill_r_done := '0';
w.state := preparewb;
when writeback =>
co.stall <= '1';
w.rvalid := '1';
mwbo.adr <=(others => '0');
mwbo.adr(ADDRESS_HIGH downto 2) <= r.writeback_tag & r.fill_line_number & r.fill_offset_w;
wb_cyc <= '1';--r.rvalid ; --'1';
wb_stb <= not r.fill_r_done;
mwbo.we <= '1';--r.rvalid; --1';
mwbo.sel <= (others => '1');
mwbo.tag(cmem_addrb'LENGTH) <= '0';
if mwbi.stall='0' and r.fill_r_done='0' then
if w.count=0 then
w.fill_r_done := '1';
else
w.fill_offset_r := std_logic_vector(unsigned(r.fill_offset_r) + 1);
w.fill_offset_w := r.fill_offset_r;
w.count := w.count - 1;
end if;
end if;
if req_last='1' and r.count=0 then
if r.in_flush='1' then
w.state := flush;
w.in_flush:='0';
else
w.fill_offset_r := r.req_offset;--(others => '0');
w.fill_offset_w := r.req_offset;--(others => '0');
w.fill_r_done := '0';
w.count := BURSTWORDS;
w.state := readline;
end if;
end if;
mwbo.dat <= cmem_dob;
cmem_addrb <= (r.fill_line_number & r.fill_offset_r) ;
cmem_enb <= not mwbi.stall;-- or not r.rvalid;
cmem_addra <= (others => DontCareValue);
cmem_web <= (others=>'0');
--cmem_wea<="0000"; -- Don't allow writes.
cmem_ena <= '0';
when preparewb =>
co.stall <= '1';
mwbo.dat <= cmem_dob;
cmem_addrb <= (r.fill_line_number & r.fill_offset_r) ;
cmem_enb <= '1';
cmem_addra <= (others => DontCareValue);
cmem_web <= (others=>'0');
cmem_ena <= '0';
w.fill_offset_r := std_logic_vector(unsigned(r.fill_offset_r) + 1);
w.count := BURSTWORDS;
w.state := writeback;
--cmem_wea<="0000"; -- Don't allow writes.
when write_after_fill =>
cmem_addra <= (others => DontCareValue);
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);
cmem_dib <= r.req_data;
cmem_web <= r.req_wmask;
cmem_enb <= '1';
cmem_ena <= '0';
cmem_dia <= (others => 'X');
cmem_wea <= (others => 'X');
co.stall <= '1';
--b_stall := '1';
valid := '0'; -- ERROR
--b_valid := '0'; -- ERROR
--w.ack_b_write := '1';
w.state := settle;
when settle =>
cmem_addra <= r.req_addr(CACHE_MAX_BITS-1 downto 2);--r.fill_tag & r.fill_line_number & r.fill_offset_w;
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);--r.fill_tag & r.fill_line_number & r.fill_offset_w;
cmem_web <= (others => '0');
cmem_wea <= (others => '0');
tmem_ena <= '1';
cmem_ena <= '1';
tmem_addra <= address_to_line_number(r.req_addr);
tmem_addrb <= address_to_line_number(r.req_addr);
co.stall <= '1';
--b_stall := '1';
tmem_web <= '0';
valid := '0'; -- ERROR
--b_valid := '0';--r.ack_b_write; -- ERROR -- note: don't ack writes
w.state := idle;
when flush =>
co.stall<='1';
valid:='0';
tmem_addrb <= r.flush_line_number;
tmem_addra <= (others => DontCareValue);
tmem_ena <='0';
tmem_wea <='0';
tmem_dib(VALIDBIT)<='0';
tmem_dib(DIRTYBIT)<='0';
tmem_web<='1';
tmem_enb<='1';
cmem_enb <= '0';
cmem_addra <= (others => DontCareValue);
cmem_addrb <= (others => DontCareValue);
cmem_dia <= (others => DontCareValue);
cmem_dib <= (others => DontCareValue);
cmem_ena <= '0';
w.flush_line_number := r.flush_line_number+1;
w.fill_offset_r := (others => '0');
w.in_flush := '1';
w.flush_req := '0';
-- w.fill_offset_r := (others => '0');
w.fill_offset_w := (others => '0');
-- only valid in next cycle
if r.in_flush='1' and tmem_dob(VALIDBIT)='1' and tmem_dob(DIRTYBIT)='1' then
-- report "Need to wb" severity note;
w.writeback_tag := tmem_dob(tag_type'RANGE); -- NOTE: can we use tmem_doa ?
--w.fill_is_b := '1';
tmem_web<='0';
w.fill_offset_r := (others => '0');
w.flush_line_number := r.flush_line_number;
w.fill_r_done := '0';
w.rvalid := '1';
w.state := preparewb;
else
w.fill_line_number := r.flush_line_number;
if r.fill_line_number = line_number_all_ones then --r.in_flush='1' and r.fill_line_number=line_number_all_zeroes then
w.state := idle;
w.in_flush :='0';
end if;
end if;
end case;
if ci.flush='1' then
w.flush_req :='1';
end if;
if syscon.rst='1' then
w.req := '0';
w.misses :=0;
w.flush_req :='1';
w.in_flush :='0';
w.req:='0';
w.req_we:='0';
--r.fill_line_number := (others => '0');
-- r.flush_line_number := (others => '0');
--r.state <= flush;
w.state := idle;
--co.valid <= '0';
end if;
if rising_edge(syscon.clk) then
--co.valid <= valid;
--co.b_valid <= b_valid;
--co.a_stall <= a_stall;
--co.b_stall <= b_stall;
r <= w;
end if;
dbg_miss<=miss;
end process;
co.err <= '0';
end behave;
| bsd-3-clause |
alvieboy/xtc-base | sim.vhd | 1 | 3086 | library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package sim is
procedure hexread(L : inout line; value:out bit_vector);
procedure hexread(L : inout line; value:out std_logic_vector);
function ishex(c : character) return boolean;
end package;
package body sim is
procedure char2hex(C: character; result: out bit_vector(3 downto 0);
good: out boolean; report_error: in boolean) is
begin
good := true;
case C is
when '0' => result := x"0";
when '1' => result := x"1";
when '2' => result := X"2";
when '3' => result := X"3";
when '4' => result := X"4";
when '5' => result := X"5";
when '6' => result := X"6";
when '7' => result := X"7";
when '8' => result := X"8";
when '9' => result := X"9";
when 'A' => result := X"A";
when 'B' => result := X"B";
when 'C' => result := X"C";
when 'D' => result := X"D";
when 'E' => result := X"E";
when 'F' => result := X"F";
when 'a' => result := X"A";
when 'b' => result := X"B";
when 'c' => result := X"C";
when 'd' => result := X"D";
when 'e' => result := X"E";
when 'f' => result := X"F";
when others =>
if report_error then
assert false report
"hexread error: read a '" & C & "', expected a hex character (0-F).";
end if;
good := false;
end case;
end;
procedure hexread(L:inout line; value:out bit_vector) is
variable OK: boolean;
variable C: character;
constant NE: integer := value'length/4; --'
variable BV: bit_vector(0 to value'length-1); --'
variable S: string(1 to NE-1);
begin
if value'length mod 4 /= 0 then --'
assert false report
"hexread Error: Trying to read vector " &
"with an odd (non multiple of 4) length";
return;
end if;
loop -- skip white space
read(L,C);
exit when ((C /= ' ') and (C /= CR) and (C /= HT));
end loop;
char2hex(C, BV(0 to 3), OK, false);
if not OK then
return;
end if;
read(L, S, OK);
-- if not OK then
-- assert false report "hexread Error: Failed to read the STRING";
-- return;
-- end if;
for I in 1 to NE-1 loop
char2hex(S(I), BV(4*I to 4*I+3), OK, false);
if not OK then
return;
end if;
end loop;
value := BV;
end hexread;
procedure hexread(L:inout line; value:out std_ulogic_vector) is
variable tmp: bit_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := TO_X01(tmp);
end hexread;
procedure hexread(L:inout line; value:out std_logic_vector) is
variable tmp: std_ulogic_vector(value'length-1 downto 0); --'
begin
hexread(L, tmp);
value := std_logic_vector(tmp);
end hexread;
function ishex(c:character) return boolean is
variable tmp : bit_vector(3 downto 0);
variable OK : boolean;
begin
char2hex(C, tmp, OK, false);
return OK;
end ishex;
end ; | bsd-3-clause |
alvieboy/xtc-base | romram.vhd | 1 | 3913 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_tag_o: out std_logic_vector(31 downto 0);
ram_wb_tag_i: in std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
ram_wb_sel_i: in std_logic_vector(3 downto 0);
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_tag_i: in std_logic_vector(31 downto 0);
rom_wb_tag_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity romram;
architecture behave of romram is
component internalram is
port (
CLKA: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(BITS-1 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
CLKB: in std_logic;
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(BITS-1 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end component;
signal rom_enable: std_logic;
signal ram_enable: std_logic;
signal romack, ramack: std_logic;
constant nothing: std_logic_vector(31 downto 0) := (others => '0');
signal rom_data: std_logic_vector(31 downto 0);
begin
rom_enable <= rom_wb_stb_i and rom_wb_cyc_i;
ram_enable <= ram_wb_stb_i and ram_wb_cyc_i;
rom_wb_stall_o <= '0';
ram_wb_stall_o <= '0';
rom_wb_ack_o <= romack;
ram_wb_ack_o <= ramack;
-- ACK processing (pipelined)
cache: if INSTRUCTION_CACHE generate
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
romack <= '0';
else
--if rom_enable='1' then
romack <= rom_enable;
if rom_enable='1' then
rom_wb_tag_o <= rom_wb_tag_i;
end if;
--end if;
end if;
end if;
end process;
end generate;
nocache: if not INSTRUCTION_CACHE generate
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
romack <= '0';
else
romack <= '1';
rom_wb_tag_o <= rom_wb_tag_i;
end if;
end if;
end process;
end generate;
-- ACK processing (pipelined)
process(ram_wb_clk_i)
begin
if rising_edge(ram_wb_clk_i) then
if ram_wb_rst_i='1' then
ramack <= '0';
else
ramack <= ram_enable;
if ram_enable='1' then
ram_wb_tag_o <= ram_wb_tag_i;
end if;
end if;
end if;
end process;
rom_wb_dat_o <= rom_data;
ram: internalram
port map (
CLKA => rom_wb_clk_i,
CLKB => ram_wb_clk_i,
WEA => '0',
ENA => rom_enable,
MASKA => "1111",
ADDRA => rom_wb_adr_i(BITS-1 downto 2),
DIA => nothing,
DOA => rom_data,
WEB => ram_wb_we_i,
ENB => ram_enable,
ADDRB => ram_wb_adr_i(BITS-1 downto 2),
DIB => ram_wb_dat_i,
MASKB => ram_wb_sel_i,
DOB => ram_wb_dat_o
);
end behave;
| bsd-3-clause |
alvieboy/xtc-base | xtccomppkg.old.vhd | 1 | 18203 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
package xtccomppkg is
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram_r is
generic (
address_bits: integer := 8;
srval_1: std_logic_vector(31 downto 0);
srval_2: std_logic_vector(31 downto 0)
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
ssra: in std_logic;
dia: in std_logic_vector(31 downto 0);
doa: out std_logic_vector(31 downto 0);
clkb: in std_logic;
enb: in std_logic;
ssrb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(31 downto 0);
dob: out std_logic_vector(31 downto 0);
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0);
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component xtc is
port (
wb_syscon: in wb_syscon_type;
-- Master wishbone interface
wbo: out wb_mosi_type;
wbi: in wb_miso_type;
-- ROM wb interface
romwbo: out wb_mosi_type;
romwbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
break: out std_logic;
intack: out std_logic;
edbg: in memory_debug_type
);
end component;
component icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
abort: in std_logic;
tag: in std_logic_vector(31 downto 0);
tagen: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_adr_o: out std_logic_vector(31 downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component mux32_4 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
i2: in std_logic_vector(31 downto 0);
i3: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
o: out std_logic_vector(31 downto 0)
);
end component;
component mux32_2 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
sel: in std_logic;
o: out std_logic_vector(31 downto 0)
);
end component mux32_2;
component alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: in alu_op_type;
en: in std_logic;
ci: in std_logic;
cen:in std_logic;
busy: out std_logic;
valid: out std_logic;
co: out std_logic;
zero: out std_logic;
ovf: out std_logic;
sign: out std_logic
);
end component;
component fetch is port (
clk: in std_logic;
rst: in std_logic;
-- Connection to ROM
stall: in std_logic;
valid: in std_logic;
address: out std_logic_vector(31 downto 0);
read: in std_logic_vector(31 downto 0);
enable: out std_logic;
strobe: out std_logic;
abort: out std_logic;
nseq: out std_logic;
-- Control
freeze: in std_logic;
jump: in std_logic;
jumpaddr: in word_type;
dual: in std_logic;
-- Outputs for next stages
fuo: out fetch_output_type
);
end component;
component decode is
port (
clk: in std_logic;
rst: in std_logic;
-- Input for previous stages
fui: in fetch_output_type;
-- Output for next stages
duo: out decode_output_type;
busy: out std_logic;
freeze: in std_logic;
flush: in std_logic;
jump: in std_logic;
jumpmsb: in std_logic;
dual: out std_logic
);
end component;
component fetchdata is
port (
clk: in std_logic;
rst: in std_logic;
-- Register access
r1_en: out std_logic;
r1_addr: out regaddress_type;
r1_read: in word_type_std;
r2_en: out std_logic;
r2_addr: out regaddress_type;
r2_read: in word_type_std;
w_addr: out regaddress_type;
w_en: out std_logic;
-- Input for previous stages
dui: in decode_output_type;
freeze: in std_logic;
flush: in std_logic;
refetch: in std_logic;
executed: in boolean;
clrhold: in std_logic;
-- Output for next stages
fduo: out fetchdata_output_type
);
end component;
component execute is
port (
clk: in std_logic;
rst: in std_logic;
mem_busy: in std_logic;
busy: out std_logic;
refetch: in std_logic;
wb_busy: in std_logic;
int: in std_logic;
intline: in std_logic_vector(7 downto 0);
nmi: in std_logic;
nmiack: out std_logic;
-- Input for previous stages
fdui: in fetchdata_output_type;
-- Output for next stages
euo: out execute_output_type;
-- Input from memory unit, for SPR update
mui: in memory_output_type;
-- Coprocessor interface
co: out copifo;
ci: in copifi;
dbgo: out execute_debug_type
);
end component execute;
component memory is
port (
clk: in std_logic;
rst: in std_logic;
-- Memory interface
wb_ack_i: in std_logic;
wb_err_i: in std_logic;
wb_dat_i: in std_logic_vector(31 downto 0);
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_o: out std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_stall_i: in std_logic;
protw: in std_logic_vector(31 downto 0);
proten: in std_logic;
busy: out std_logic;
refetch: out std_logic;
dbgo: out memory_debug_type;
-- Input for previous stages
eui: in execute_output_type;
-- Output for next stages
muo: out memory_output_type
);
end component memory;
component writeback is
port (
clk: in std_logic;
rst: in std_logic;
busy: out std_logic;
-- Register 0 access writeback
r0_en: out std_logic;
r0_we: out std_logic;
r0_addr: out regaddress_type;
r0_write: out word_type_std;
-- Register 1 access writeback
r1_en: out std_logic;
r1_we: out std_logic;
r1_addr: out regaddress_type;
r1_write: out word_type_std;
-- Input for previous stages
mui: in memory_output_type;
eui: in execute_output_type
);
end component;
component regbank_2p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_wr: in std_logic_vector(31 downto 0);
rb2_we: in std_logic;
rb2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component regbank_3p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_wr: in std_logic_vector(31 downto 0);
rb3_we: in std_logic;
rb3_en: in std_logic
-- RTL Debug access
--dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
--dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component opdec is
port (
opcode_low: in std_logic_vector(15 downto 0);
opcode_high: in std_logic_vector(15 downto 0);
dec: out opdec_type
);
end component;
component taint is
generic (
COUNT: integer := 16
);
port (
clk: in std_logic;
rst: in std_logic;
req1_en: in std_logic;
req1_r: in regaddress_type;
req2_en: in std_logic;
req2_r: in regaddress_type;
ready: out std_logic;
set_en: in std_logic;
set_r: in regaddress_type;
clr_en: in std_logic;
clr_r: in regaddress_type;
taint: out std_logic_vector(COUNT-1 downto 0)
);
end component;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end component;
component xtc_wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_syscon: in wb_syscon_type;
-- Master 0 signals
m0_wbi: in wb_mosi_type;
m0_wbo: out wb_miso_type;
-- Master 1 signals
m1_wbi: in wb_mosi_type;
m1_wbo: out wb_miso_type;
-- Slave signals
s0_wbi: in wb_miso_type;
s0_wbo: out wb_mosi_type
);
end component;
component wb_master_p_to_slave_np is
port (
syscon: in wb_syscon_type;
-- Master signals
mwbi: in wb_mosi_type;
mwbo: out wb_miso_type;
-- Slave signals
swbi: in wb_miso_type;
swbo: out wb_mosi_type
);
end component;
component xtc_top_bram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type
);
end component;
component xtc_top_sdram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type;
-- DMA
dmawbi: in wb_mosi_type;
dmawbo: out wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component;
component regbank_5p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw_wr: in std_logic_vector(31 downto 0);
rbw_we: in std_logic;
rbw_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component regbank_5p;
component regbank_4r_2w is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw1_wr: in std_logic_vector(31 downto 0);
rbw1_we: in std_logic;
rbw1_en: in std_logic;
rbw2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw2_wr: in std_logic_vector(31 downto 0);
rbw2_we: in std_logic;
rbw2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component insnqueue is
port (
rst: in std_logic;
clkw: in std_logic;
din: in std_logic_vector(15 downto 0);
en: in std_logic;
clr: in std_logic;
full: out std_logic;
clkr: in std_logic;
pop: in std_logic;
dualpop: in std_logic;
dout0: out std_logic_vector(15 downto 0);
dout1: out std_logic_vector(15 downto 0);
empty: out std_logic;
dvalid: out std_logic
);
end component;
component xtc_ioctrl is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
-- Slaves
swbi: in slot_wbi;
swbo: out slot_wbo;
sids: in slot_ids
);
end component xtc_ioctrl;
component mmu is
generic (
TLB_ENTRY_BITS: natural := 3;
CONTEXT_SIZE_BITS: natural := 6;
SIMPLIFIED: boolean := true
);
port (
clk: in std_logic;
rst: in std_logic;
addr: in std_logic_vector(31 downto 0);
ctx: in std_logic_vector(CONTEXT_SIZE_BITS-1 downto 0);
en: in std_logic;
tlbw: in std_logic;
tlba: in std_logic_vector(TLB_ENTRY_BITS-1 downto 0);
tlbv: in tlb_entry_type;
paddr: out std_logic_vector(31 downto 0);
valid: out std_logic;
pw: out std_logic; -- Write permission
pr: out std_logic; -- Read permission
px: out std_logic; -- eXecute permission
ps: out std_logic -- Supervisor/User
);
end component;
component dcache is
generic (
ADDRESS_HIGH: integer := 31;
CACHE_MAX_BITS: integer := 13; -- 8 Kb
CACHE_LINE_SIZE_BITS: integer := 6 -- 64 bytes
);
port (
syscon: in wb_syscon_type;
ci: in dcache_in_type;
co: out dcache_out_type;
mwbi: in wb_miso_type;
mwbo: out wb_mosi_type
);
end component;
component generic_dp_ram_rf is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component nodev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end component;
component sinkdev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end component;
end package;
| bsd-3-clause |
shvorin/pcie-emu | hdllib/common/util.vhd | 1 | 13658 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
-- This package contains common types and functions; not router-specific stuff.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc;
use work.types.all;
package util is
function maximum(constant t1, t2 : natural) return natural;
function maximum(constant a : integer_array) return integer;
function minimum(constant t1, t2 : natural) return natural;
function minimum(constant t1, t2 : std_logic_vector) return std_logic_vector;
function minimum(constant a : integer_array) return integer;
-- nearly the same as UNSIGNED_NUM_BITS from ieee.numeric_bit
-- NB: UNSIGNED_NUM_BITS seem to be incorrect ;)
function ceil_log2 (constant x : positive) return natural;
function nor_reduce(v : std_logic_vector) return std_logic;
function or_reduce(v : std_logic_vector) return std_logic;
function and_reduce(v : std_logic_vector) return std_logic;
function nand_reduce(v : std_logic_vector) return std_logic;
function nor_reduce(v : std_logic_vector) return boolean;
function or_reduce(v : std_logic_vector) return boolean;
function and_reduce(v : std_logic_vector) return boolean;
function nand_reduce(v : std_logic_vector) return boolean;
-- "unary logarithm": finds the highest set bit and drops all other bits;
-- if argument is zero the result is also zero
function unary_log (constant v : std_logic_vector) return std_logic_vector;
function "and" (constant arg : std_logic_vector; constant s : std_logic)
return std_logic_vector;
-- encodes bit range into binary representation (i.e. returns the number of
-- (the only) lit bit, otherwise result is meaningless). FIXME: why to
-- (re-)implement a simple library function?!
function encode (constant arg : std_logic_vector) return natural;
function to_stdl (constant v : in boolean) return std_logic;
-- drop all bits except the lowest fired
function lowest_fired (arg : std_logic_vector) return std_logic_vector;
function invert(arg : std_logic_vector) return std_logic_vector;
function singleton(arg : std_logic) return std_logic_vector;
function align2_down(v : std_logic_vector) return std_logic_vector;
function align8_down(v : std_logic_vector) return std_logic_vector;
function align8_up(v : std_logic_vector) return std_logic_vector;
-- treat segment descriptor
function desc2mask(x : std_logic_vector) return std_logic_vector;
function desc2base(x : std_logic_vector) return std_logic_vector;
--
-- optimized version; hint_logsize must be guaranteed to be no greater than
-- actual logsize
function desc2mask(x : std_logic_vector; hint_logsize : natural; exact : boolean := false) return std_logic_vector;
function desc2base(x : std_logic_vector; hint_logsize : natural; exact : boolean := false) return std_logic_vector;
function extend64(v : std_logic_vector) return qword;
function extend64(i : integer) return qword;
function extend(size : natural; v : std_logic_vector) return std_logic_vector;
-- from std_logic_1164_additions
function to_hstring (value : std_ulogic_vector) return string;
function to_hstring (value : std_logic_vector) return string;
function reverse(x : std_logic_vector) return std_logic_vector;
end util;
package body util is
function ceil_log2 (constant x : positive)
return natural is
function hlp (constant x : natural) return natural is
begin
if x < 1 then
return 0;
else
return 1 + hlp(x/2);
end if;
end;
begin -- ceil_log2
return hlp(x-1);
end ceil_log2;
function nor_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.nor_reduce(v);
end;
function or_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.or_reduce(v);
end;
function and_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.and_reduce(v);
end;
function nand_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.nand_reduce(v);
end;
function nor_reduce(v : std_logic_vector) return boolean is
begin
return nor_reduce(v) = '1';
end;
function or_reduce(v : std_logic_vector) return boolean is
begin
return or_reduce(v) = '1';
end;
function and_reduce(v : std_logic_vector) return boolean is
begin
return and_reduce(v) = '1';
end;
function nand_reduce(v : std_logic_vector) return boolean is
begin
return nand_reduce(v) = '1';
end;
function unary_log (constant v : std_logic_vector)
return std_logic_vector is
alias u : std_logic_vector(v'high downto v'low) is v;
variable result : std_logic_vector(u'range);
begin
for i in u'range loop
if i = u'high then
result(i) := u(i);
else
result(i) := u(i) and nor_reduce(u(u'high downto i+1)); -- FIXME
end if;
end loop; -- i
return result;
end unary_log;
function maximum (constant t1, t2 : natural) return natural is
begin
if t1 > t2 then return t1; else return t2; end if;
end maximum;
function maximum (constant a : integer_array) return integer is
variable result : integer := a(a'low);
begin
for i in a'range loop
if a(i) > result then
result := a(i);
end if;
end loop;
return result;
end;
function minimum (constant t1, t2 : natural) return natural is
begin
if t1 < t2 then return t1; else return t2; end if;
end minimum;
function minimum (constant t1, t2 : std_logic_vector) return std_logic_vector is
begin
if t1 < t2 then return t1; else return t2; end if;
end;
function minimum (constant a : integer_array) return integer is
variable result : integer := a(a'low);
begin
for i in a'range loop
if a(i) < result then
result := a(i);
end if;
end loop;
return result;
end;
function "and" (constant arg : std_logic_vector; constant s : std_logic)
return std_logic_vector is
variable result : std_logic_vector(arg'range);
begin -- "and"
for i in arg'range loop
result(i) := arg(i) and s;
end loop; -- i
return result;
end "and";
function encode (constant arg : std_logic_vector) return natural is
alias xarg : std_logic_vector(0 to arg'length-1) is arg;
constant sz : natural := ceil_log2(xarg'length);
variable result : std_logic_vector(sz-1 downto 0);
variable sum : std_logic;
variable b, p : natural;
variable t : natural := 1;
begin
for i in 0 to sz-1 loop
b := t;
t := 2 * t;
p := t;
sum := '0';
eval_result_i : loop
exit when b > xarg'high;
sum := sum or not nor_reduce(xarg(xarg'low + b
to xarg'low + minimum(p-1, xarg'high)));
b := b + t;
p := p + t;
end loop eval_result_i;
result(i) := sum;
end loop; -- i
return conv_integer(result);
end;
function to_stdl (constant v : in boolean) return std_logic is
begin
if v then
return '1';
else
return '0';
end if;
end;
function lowest_fired (arg : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(arg'range);
function no_competitors(i : integer) return std_logic is
begin
if i = arg'low then
return '1';
end if;
if arg'ascending then
return nor_reduce(arg(arg'low to i-1));
else
return nor_reduce(arg(i-1 downto arg'low));
end if;
end;
begin
for i in arg'range loop
result(i) := arg(i) and no_competitors(i);
end loop;
return result;
end;
function invert(arg : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(arg'range);
begin
for i in arg'range loop
result(i) := arg(arg'left + arg'right - i);
end loop;
return result;
end;
function singleton(arg : std_logic) return std_logic_vector is
begin
return (0 => arg);
end;
function align8_down(v : std_logic_vector) return std_logic_vector is
begin
return v(v'high downto v'low + 3) & "000";
end;
function align2_down(v : std_logic_vector) return std_logic_vector is
begin
return v(v'high downto v'low + 1) & "0";
end;
function align8_up(v : std_logic_vector) return std_logic_vector is
constant v1 : std_logic_vector(v'range) := v + "111";
begin
return v1(v'high downto v'low + 3) & "000";
end;
-- treat segment descriptor
function desc2mask(x : std_logic_vector) return std_logic_vector is
begin
return (x-1) xor x;
end;
function desc2base(x : std_logic_vector) return std_logic_vector is
begin
return (x-1) and x;
end;
function desc2mask(x : std_logic_vector; hint_logsize : natural; exact : boolean := false)
return std_logic_vector
is
subtype hi_range is integer range x'high downto x'low + hint_logsize;
subtype lo_range is integer range x'low + hint_logsize - 1 downto x'low;
variable result : std_logic_vector(x'range);
begin
result(lo_range) := (others => '1');
if exact then
result(hi_range) := (others => '0');
else
result(hi_range) := desc2mask(x(hi_range));
end if;
return result;
end;
function desc2base(x : std_logic_vector; hint_logsize : natural; exact : boolean := false)
return std_logic_vector
is
constant tail : std_logic_vector(hint_logsize - 1 downto 0) := (others => '0');
begin
if exact then
return x(x'high downto x'low + hint_logsize) & tail;
else
return desc2base(x(x'high downto x'low + hint_logsize)) & tail;
end if;
end;
function extend64(v : std_logic_vector) return qword is
variable result : qword := (others => '0');
begin
result(v'length - 1 downto 0) := v;
return result;
end;
function extend64(i : integer) return qword is
begin
return conv_std_logic_vector(i, 64);
end;
function extend(size : natural; v : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(size - 1 downto 0) := (others => '0');
begin
result(v'length - 1 downto 0) := v;
return result;
end;
function to_hstring (value : std_ulogic_vector) return string is
constant ne : integer := (value'length+3)/4;
variable pad : std_ulogic_vector(0 to (ne*4 - value'length) - 1);
variable ivalue : std_ulogic_vector(0 to ne*4 - 1);
variable result : string(1 to ne);
variable quad : std_ulogic_vector(0 to 3);
begin
if value'length < 1 then
return "";
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_hstring (value : std_logic_vector) return string is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function reverse(x : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(x'range);
begin
for i in x'range loop
result(i) := x(x'high + x'low - i);
end loop;
return result;
end;
end util;
| bsd-3-clause |
alvieboy/xtc-base | nodev.vhd | 1 | 739 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity nodev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end entity nodev;
architecture behave of nodev is
signal ack,err: std_logic := '0';
begin
wbo.ack<=ack;
wbo.err<=err;
wbo.dat<=(others => 'X');
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
ack<='0';
err<='0';
else
ack<='0';
err<='0';
if err='0' and wbi.stb='1' and wbi.cyc='1' then
--ack<='1';
err<='1';
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause |
alvieboy/xtc-base | tx_unit_sim.vhd | 1 | 5222 | ------------------------------------------------------------------------------
---- ----
---- RS-232 simple Tx module ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- Implements a simple 8N1 tx module for RS-232. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Philippe Carton, philippe.carton2 libertysurf.fr ----
---- - Juan Pablo Daniel Borgna, jpdborgna gmail.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2001-2003 Philippe Carton ----
---- Copyright (c) 2005 Juan Pablo Daniel Borgna ----
---- Copyright (c) 2005-2008 Salvador E. Tropea ----
---- Copyright (c) 2005-2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the GPL license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: TxUnit(Behaviour) (Entity and architecture) ----
---- File name: Txunit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- zpu.UART ----
---- Target FPGA: Spartan ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.pty.all;
entity TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- In transmit
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end entity TxUnit;
architecture Behaviour of TxUnit is
signal tbuff_r : std_logic_vector(7 downto 0); -- transmit buffer
signal t_r : std_logic_vector(7 downto 0); -- transmit register
signal loaded_r : std_logic:='0'; -- Buffer loaded
signal txd_r : std_logic:='1'; -- Tx buffer ready
signal lixo: integer;
begin
intx_o <= '0';
busy_o <= '0';--load_i or loaded_r;
txd_o <= txd_r;
-- Tx process
TxProc:
process (clk_i)
variable bitpos : integer range 0 to 10; -- Bit position in the frame
variable txint: integer;
variable txresult: integer;
begin
if rising_edge(clk_i) then
if reset_i='1' then
loaded_r <= '0';
bitpos:=0;
txd_r <= '1';
else -- reset_i='0'
if load_i='1' then
--report "kkkk";
txint := conv_integer( unsigned(datai_i) );
txresult := pty_transmit(txint);
end if; -- enable_i='1'
end if; -- reset_i='0'
end if; -- rising_edge(clk_i)
end process TxProc;
process
variable c: integer;
begin
c := pty_initialize;
wait;
end process;
end architecture Behaviour;
| bsd-3-clause |
alvieboy/xtc-base | xtc_top_ppro_sdram.vhd | 1 | 6923 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_top_ppro_sdram is
port (
CLK: in std_logic;
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
-- SPI flash
MOSI: out std_logic;
MISO: in std_logic;
SCK: out std_logic;
NCS: out std_logic;
--NNMI: in std_logic;
-- SD card
SDMOSI: out std_logic;
SDMISO: in std_logic;
SDSCK: out std_logic;
SDNCS: out std_logic;
HSYNC: out std_logic;
VSYNC: out std_logic;
BLUE: out std_logic_vector(3 downto 0);
GREEN: out std_logic_vector(3 downto 0);
RED: out std_logic_vector(3 downto 0);
JOY_FIRE2: in std_logic;
JOY_FIRE1: in std_logic;
JOY_LEFT: in std_logic;
JOY_RIGHT: in std_logic;
JOY_SEL: in std_logic;
JOY_UP: in std_logic;
JOY_DOWN: in std_logic;
AUDIO: out std_logic_vector(1 downto 0);
RESET: in std_logic
-- The LED
--LED: out std_logic
);
end entity xtc_top_ppro_sdram;
architecture behave of xtc_top_ppro_sdram is
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal clk_off_3ns: std_ulogic;
signal wbi: wb_mosi_type;
signal wbo: wb_miso_type;
signal dmawbi: wb_mosi_type;
signal dmawbo: wb_miso_type;
signal syscon: wb_syscon_type;
signal swbi: slot_wbi;
signal swbo: slot_wbo;
signal sids: slot_ids;
signal nmi, nmi_q, nmiack, rstreq,rstreq_q, do_reset: std_logic;
signal vgaclk: std_logic;
begin
AUDIO(0) <= '0';
AUDIO(1) <= '0';
process(sysclk)
begin
if rising_edge(sysclk) then
if sysrst='1' then
rstreq_q<='0';
else
rstreq_q<=rstreq;
end if;
end if;
end process;
do_reset<='1' when rstreq_q='0' and rstreq='1' else '0';
syscon.clk<=sysclk;
syscon.rst<=sysrst or do_reset;
cpu: entity work.xtc_top_sdram
port map (
wb_syscon => syscon,
iowbi => wbo,
iowbo => wbi,
nmi => nmi,
nmiack => nmiack,
rstreq => rstreq,
dmawbi => dmawbi,
dmawbo => dmawbo,
-- extra clocking
clk_off_3ns => clk_off_3ns,
-- SDRAM signals
DRAM_ADDR => DRAM_ADDR(11 downto 0),
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
--DRAM_ADDR(12)<='0';
ioctrl: entity work.xtc_ioctrl
port map (
syscon => syscon,
wbi => wbi,
wbo => wbo,
swbi => swbi,
swbo => swbo,
sids => sids
);
myrom: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(0),
wbo => swbi(0)
);
myuart: entity work.uart
generic map (
bits => 11
)
port map (
syscon => syscon,
wbi => swbo(1),
wbo => swbi(1),
tx => TXD,
rx => RXD
);
flashspi: entity work.spi
generic map (
INTERNAL_SPI => true
)
port map (
syscon => syscon,
wbi => swbo(2),
wbo => swbi(2),
mosi => MOSI,
miso => MISO,
sck => SCK,
cs => NCS
);
sdspi: entity work.spi
generic map (
INTERNAL_SPI => false
)
port map (
syscon => syscon,
wbi => swbo(3),
wbo => swbi(3),
mosi => SDMOSI,
miso => SDMISO,
sck => SDSCK,
cs => SDNCS
);
vgaenabled: if false generate
vga: entity work.vga_320_240_idx
port map (
wb_clk_i => syscon.clk,
wb_rst_i => syscon.rst,
wb_dat_o => swbi(4).dat,
wb_dat_i => swbo(4).dat,
wb_adr_i => swbo(4).adr(31 downto 2),
wb_we_i => swbo(4).we,
wb_cyc_i => swbo(4).cyc,
wb_stb_i => swbo(4).stb,
wb_ack_o => swbi(4).ack,
-- Wishbone MASTER interface
mi_wb_dat_i => dmawbo.dat,
mi_wb_dat_o => dmawbi.dat,
mi_wb_adr_o => dmawbi.adr,
mi_wb_sel_o => dmawbi.sel,
--mi_wb_cti_o => dmawbi.cti,
mi_wb_we_o => dmawbi.we,
mi_wb_cyc_o => dmawbi.cyc,
mi_wb_stb_o => dmawbi.stb,
mi_wb_ack_i => dmawbo.ack,
mi_wb_stall_i => dmawbo.stall,
-- VGA signals
vgaclk => vgaclk,
vga_hsync => HSYNC,
vga_vsync => VSYNC,
vga_b(0) => open,
vga_b(4 downto 1) => BLUE,
vga_r(0) => open,
vga_r(4 downto 1) => RED,
vga_g(0) => open,
vga_g(4 downto 1) => GREEN,
blank => open
);
end generate;
vgadisabled: if true generate
eslot: entity work.sinkdev
port map (
syscon => syscon,
wbi => swbo(4),
wbo => swbi(4)
);
dmawbi.dat <= (others => 'X');
dmawbi.adr <= (others => 'X');
dmawbi.sel <= (others => 'X');
dmawbi.we <='0';
dmawbi.cyc<='0';
dmawbi.stb<='0';
RED<=(others => '0');
GREEN<=(others => '0');
BLUE<=(others => '0');
HSYNC<='0';
VSYNC<='0';
end generate;
emptyslots: for N in 5 to 15 generate
eslot: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(N),
wbo => swbi(N)
);
--swbi(N) <= wb_miso_default;
end generate;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
rstgen: entity work.xtc_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => RXD,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: entity work.clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout1 => clk_off_3ns,
vgaclk => vgaclk,
rstout => clkgen_rst
);
-- NMI
process (sysclk)
begin
if rising_edge(sysclk) then
if sysrst='1' then
nmi <= '0';
else
if RESET='1' then
nmi<='1';
elsif nmiack='1' then
nmi<='0';
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause |
alvieboy/xtc-base | wishbonepkg.vhd | 1 | 1479 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wishbonepkg is
constant CTI_CYCLE_CLASSIC: std_logic_vector(2 downto 0) := "000";
constant CTI_CYCLE_CONSTADDR: std_logic_vector(2 downto 0) := "001";
constant CTI_CYCLE_INCRADDR: std_logic_vector(2 downto 0) := "010";
constant CTI_CYCLE_ENDOFBURST: std_logic_vector(2 downto 0) := "111";
constant BTE_BURST_LINEAR: std_logic_vector(1 downto 0) := "00";
constant BTE_BURST_4BEATWRAP: std_logic_vector(1 downto 0) := "01";
constant BTE_BURST_8BEATWRAP: std_logic_vector(1 downto 0) := "10";
constant BTE_BURST_16BEATWRAP: std_logic_vector(1 downto 0) := "11";
type wb_miso_type is record
ack: std_logic;
dat: std_logic_vector(31 downto 0);
tag: std_logic_vector(31 downto 0);
int: std_logic;
err: std_logic;
rty: std_logic;
stall: std_logic;
end record;
type wb_mosi_type is record
dat: std_logic_vector(31 downto 0);
adr: std_logic_vector(31 downto 0);
tag: std_logic_vector(31 downto 0);
cyc: std_logic;
stb: std_logic;
sel: std_logic_vector(3 downto 0);
cti: std_logic_vector(2 downto 0);
bte: std_logic_vector(1 downto 0);
we: std_logic;
-- Not in wishbone standard
--bse: std_logic_vector(5 downto 0); -- Burst size extension
end record;
type wb_syscon_type is record
clk: std_logic;
rst: std_logic;
end record;
end wishbonepkg;
| bsd-3-clause |
SteffenReith/J1Sc | vprj/vhdl/J1Sc/J1Sc/J1Sc.srcs/sources_1/imports/J1Sc/src/main/vhdl/arch/Nexys4DDR/Board_Nexys4DDR.vhd | 2 | 3813 | --------------------------------------------------------------------------------
--
-- Creation Date: Fri Apr 7 16:00:52 GMT+2 2017
-- Creator: Steffen Reith
-- Module Name: Board_Nexys4DDR - Behavioral
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
-- Remark: The pmod pins are renumberd as follows 1 -> 0, 2 -> 1, 3 -> 2,
-- 4 -> 3, 7 -> 4, 8 -> 5, 9 -> 6, 10 -> 7
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity Board_Nexys4DDR is
port (nreset : in std_logic;
clk100Mhz : in std_logic;
extInt : in std_logic_vector(0 downto 0);
leds : out std_logic_vector(15 downto 0);
rgbLeds : out std_logic_vector(5 downto 0);
segments_a : out std_logic;
segments_b : out std_logic;
segments_c : out std_logic;
segments_d : out std_logic;
segments_e : out std_logic;
segments_f : out std_logic;
segments_g : out std_logic;
dot : out std_logic;
selector : out std_logic_vector(7 downto 0);
pmodA : inout std_logic_vector(7 downto 0);
sSwitches : in std_logic_vector(15 downto 0);
pButtons : in std_logic_vector(4 downto 0);
tck : in std_logic;
tms : in std_logic;
tdi : in std_logic;
tdo : out std_logic;
rx : in std_logic;
tx : out std_logic);
end Board_Nexys4DDR;
architecture Structural of Board_Nexys4DDR is
-- Positive reset signal
signal reset : std_logic;
-- Signals related to the board clk
signal boardClk : std_logic;
signal boardClkLocked : std_logic;
-- Interface for PModA
signal pmodA_read : std_logic_vector(7 downto 0);
signal pmodA_write : std_logic_vector(7 downto 0);
signal pmodA_writeEnable : std_logic_vector(7 downto 0);
begin
-- Instantiate a PLL/MMCM (makes a 80Mhz clock)
makeClk : entity work.PLL(Structural)
port map (clkIn => clk100Mhz,
clkOut => boardClk,
isLocked => boardClkLocked);
-- Make the reset positive
reset <= not nreset;
-- Instantiate the J1SoC core created by Spinal
core : entity work.J1Nexys4X
port map (reset => reset,
boardClk => boardClk,
boardClkLocked => boardClkLocked,
extInt => extInt,
leds => leds,
rgbLeds => rgbLeds,
segments_a => segments_a,
segments_b => segments_b,
segments_c => segments_c,
segments_d => segments_d,
segments_e => segments_e,
segments_f => segments_f,
segments_g => segments_g,
dot => dot,
selector => selector,
pmodA_read => pmodA_read,
pmodA_write => pmodA_write,
pmodA_writeEnable => pmodA_writeEnable,
sSwitches => sSwitches,
pButtons => pButtons,
tck => tck,
tms => tms,
tdi => tdi,
tdo => tdo,
rx => rx,
tx => tx);
-- Connect the pmodA read port
pmodA_read <= pmodA;
-- generate the write port and equip it with tristate functionality
pmodAGen : for i in pmodA'range generate
pmodA(i) <= pmodA_write(i) when pmodA_writeEnable(i) = '1' else 'Z';
end generate;
end architecture;
| bsd-3-clause |
SteffenReith/J1Sc | src/main/vhdl/arch/Nexys4/PLL.vhd | 1 | 6106 | --------------------------------------------------------------------------------
-- Author: Steffen Reith ([email protected])
--
-- Creation Date: Tue Jan 17 19:29:25 GMT+1 2017
-- Creator: Steffen Reith
-- Module Name: PLL - Structural
-- Project Name: J1Sc - A simple J1 implementation in Scala using Spinal HDL
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity PLL is
port (clkIn : in std_logic;
clkOut : out std_logic;
isLocked : out std_logic);
end PLL;
architecture Structural of PLL is
-- Control signals
signal locked : std_logic; -- The MMCM has achieved phase alignment
signal psDone_unused : std_logic; -- Dummy signal for phase shift done
signal clkinstopped_unused : std_logic; -- Input clock has stopped (not used)
signal clkfbstopped_unused : std_logic; -- Feedback clock has stopped (not used)
signal drdy_unused : std_logic; -- Reconfiguration ready signal
signal do_unused : std_logic_vector(15 downto 0); -- Reconfiguration data out
-- Internal clock signals
signal clkInI : std_logic; -- Internal buffered input clock
signal clkI1 : std_logic; -- Internal output clock 1
signal clkOutI1 : std_logic; -- Internal already buffered output clock 1
signal clkDI_unused : std_logic; -- Internal delayed output clock
-- Feedback clock signals
signal clkfbI : std_logic; -- Internal unbuffered feedback clock
signal clkfbIBuf : std_logic; -- Internal buffered feedback clock
-- Unused clock ports
signal clkfbb_unused : std_logic;
signal clk0b_unused : std_logic;
signal clk1b_unused : std_logic;
signal clk2_unused : std_logic;
signal clk2b_unused : std_logic;
signal clk3_unused : std_logic;
signal clk3b_unused : std_logic;
signal clk4_unused : std_logic;
signal clk5_unused : std_logic;
signal clk6_unused : std_logic;
begin
-- Instantiate a input clock buffer
clkInBuffer : IBUFG
port map (O => clkInI,
I => clkIn);
-- Instantiate a clock buffer for the internal feedback signal
feedbackBuffer : BUFG
port map (O => clkfbIBuf,
I => clkfbI);
-- Instantiate a clock manager
clkgen : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED", -- MMCM programming affecting jitter
CLKOUT4_CASCADE => false, -- don't divide output more than 128
COMPENSATION => "ZHOLD", -- Clk input compensation for feedback
STARTUP_WAIT => false, -- not supported yet (set to default)
DIVCLK_DIVIDE => 1, -- Division ratio for output clocks
CLKFBOUT_MULT_F => 10.000, -- set feedback base
CLKFBOUT_PHASE => 0.000, -- phase of feedback output
CLKFBOUT_USE_FINE_PS => false, -- Don't enable fine shift
--CLKOUT0_DIVIDE_F => 12.500, -- Scale clock to 80Mhz
CLKOUT0_DIVIDE_F => 10.000, -- Scale to 100Mhz
CLKOUT0_PHASE => 0.000, -- Phase of clock 0 (no shift)
CLKOUT0_DUTY_CYCLE => 0.500, -- Duty cycle of clock 0
CLKOUT0_USE_FINE_PS => false, -- No fine shift for clock 0
CLKOUT1_DIVIDE => 10, -- Scale clock 1 to 1.0
CLKOUT1_PHASE => 270.000, -- Phase of clock 1 (delayed)
CLKOUT1_DUTY_CYCLE => 0.500, -- Duty cycle of clock 1
CLKOUT1_USE_FINE_PS => false, -- No fine shift for clock 1
CLKIN1_PERIOD => 10.000, -- 10ns input clock period -> 100Mhz
REF_JITTER1 => 0.010) -- Set expected jitter to default
port map (
CLKFBOUT => clkfbI,
CLKFBOUTB => clkfbb_unused, -- Unused inverted feedback
-- Output clocks (delayed and non inverted)
CLKOUT0 => clkI1,
CLKOUT0B => clk0b_unused,
CLKOUT1 => clkDI_unused,
CLKOUT1B => clk1b_unused,
-- Unused clocks
CLKOUT2 => clk2_unused,
CLKOUT2B => clk2b_unused,
CLKOUT3 => clk3_unused,
CLKOUT3B => clk3b_unused,
CLKOUT4 => clk4_unused,
CLKOUT5 => clk5_unused,
CLKOUT6 => clk6_unused,
-- Input clock control
CLKFBIN => clkfbIBuf, -- Buffered feedback signal
CLKIN1 => clkInI, -- Input clock
CLKIN2 => '0', -- Second input clock is not used
CLKINSEL => '1', -- Select primary input clock
-- Disable dynamic reconfiguration
DADDR => (others => '0'), -- set all address bits to 0
DCLK => '0', -- No clock for the reconfig port
DEN => '0', -- Disable to reconfiguration port
DI => (others => '0'), -- set reconfiguration data to 0
DO => do_unused, -- Ignore MMCM reconfig data output
DRDY => drdy_unused, -- Ignore the ready signal
DWE => '0', -- Disable the write enable
-- Don't implement dynamic phase shift
PSCLK => '0', -- No phase shift clock
PSEN => '0', -- Disable phase shift
PSINCDEC => '0', -- No inc / dec of phase shift
PSDONE => psDone_unused, -- Dummy signal for phase shift done
-- Other control and status signals
LOCKED => locked, -- MMCE clock is stable
CLKINSTOPPED => clkinstopped_unused, -- Input clock has stopped (not used)
CLKFBSTOPPED => clkfbstopped_unused, -- Feedback clock has stopped (not used)
PWRDWN => '0', -- Don't power down MMCE
RST => '0'); -- No reset after startup
-- Scaled clock
clk1Buf : BUFGCE
port map (O => clkOutI1,
CE => locked,
I => clkI1);
clkOut <= clkOutI1;
-- Provide the locked signal to the outside world
isLocked <= locked;
end architecture;
| bsd-3-clause |
INTI-CMNB-FPGA/fpga_lib | vhdl/numeric/testbench/numeric_tb.vhdl | 1 | 5137 | --
-- Numeric testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Numeric.all;
use FPGALIB.Simul.all;
entity Numeric_tb is
end entity Numeric_tb;
architecture Testbench of Numeric_tb is
begin
test: process
begin
print("* Testing minimum and maximum");
assert minimum(2,9)=2 report "minimum fail" severity failure;
assert maximum(2,9)=9 report "maximum fail" severity failure;
print("* Testing clog2");
assert clog2(1)=0 report "clog2(1) fail" severity failure;
assert clog2(2)=1 report "clog2(2) fail" severity failure;
assert clog2(3)=2 report "clog2(3) fail" severity failure;
assert clog2(4)=2 report "clog2(4) fail" severity failure;
assert clog2(5)=3 report "clog2(5) fail" severity failure;
assert clog2(6)=3 report "clog2(6) fail" severity failure;
assert clog2(7)=3 report "clog2(7) fail" severity failure;
assert clog2(8)=3 report "clog2(8) fail" severity failure;
assert clog2(9)=4 report "clog2(9) fail" severity failure;
assert clog2(1e3)=10 report "clog2(1e3) fail" severity failure;
assert clog2(1e4)=14 report "clog2(1e4) fail" severity failure;
assert clog2(1e5)=17 report "clog2(1e5) fail" severity failure;
assert clog2(1e9)=30 report "clog2(1e9) fail" severity failure;
print("* Testing convesions");
assert to_integer("00001001")=9 report "to_integer of 00001001 must be 9" severity failure;
assert to_integer('1')=1 report "to_integer of 1 must be 1" severity failure;
assert to_natural("00001001")=9 report "to_natural of 00001001 must be 9" severity failure;
assert to_logic(1)='1' report "to_logic of 1 must be 1" severity failure;
assert to_vector(9,8)="00001001" report "to_vector of 9 must be 00001001" severity failure;
print("* Testing Binary to Gray convesion");
assert bin2gray("0000")="0000" report "bin 0000 must be gray 0000" severity failure;
assert bin2gray("0001")="0001" report "bin 0001 must be gray 0001" severity failure;
assert bin2gray("0010")="0011" report "bin 0010 must be gray 0011" severity failure;
assert bin2gray("0011")="0010" report "bin 0011 must be gray 0010" severity failure;
assert bin2gray("0100")="0110" report "bin 0100 must be gray 0110" severity failure;
assert bin2gray("0101")="0111" report "bin 0101 must be gray 0111" severity failure;
assert bin2gray("0110")="0101" report "bin 0110 must be gray 0101" severity failure;
assert bin2gray("0111")="0100" report "bin 0111 must be gray 0100" severity failure;
assert bin2gray("1000")="1100" report "bin 1000 must be gray 1100" severity failure;
assert bin2gray("1001")="1101" report "bin 1001 must be gray 1101" severity failure;
assert bin2gray("1010")="1111" report "bin 1010 must be gray 1111" severity failure;
assert bin2gray("1011")="1110" report "bin 1011 must be gray 1110" severity failure;
assert bin2gray("1100")="1010" report "bin 1100 must be gray 1100" severity failure;
assert bin2gray("1101")="1011" report "bin 1101 must be gray 1101" severity failure;
assert bin2gray("1110")="1001" report "bin 1110 must be gray 1110" severity failure;
assert bin2gray("1111")="1000" report "bin 1111 must be gray 1000" severity failure;
print("* Testing Gray to Binary convesion");
assert gray2bin("0000")="0000" report "bin 0000 must be gray 0000" severity failure;
assert gray2bin("0001")="0001" report "bin 0001 must be gray 0001" severity failure;
assert gray2bin("0011")="0010" report "bin 0011 must be gray 0010" severity failure;
assert gray2bin("0010")="0011" report "bin 0010 must be gray 0011" severity failure;
assert gray2bin("0110")="0100" report "bin 0110 must be gray 0100" severity failure;
assert gray2bin("0111")="0101" report "bin 0111 must be gray 0101" severity failure;
assert gray2bin("0101")="0110" report "bin 0101 must be gray 0110" severity failure;
assert gray2bin("0100")="0111" report "bin 0100 must be gray 0111" severity failure;
assert gray2bin("1100")="1000" report "bin 1100 must be gray 0000" severity failure;
assert gray2bin("1101")="1001" report "bin 1101 must be gray 0001" severity failure;
assert gray2bin("1111")="1010" report "bin 1111 must be gray 0010" severity failure;
assert gray2bin("1110")="1011" report "bin 1110 must be gray 0011" severity failure;
assert gray2bin("1010")="1100" report "bin 1010 must be gray 0100" severity failure;
assert gray2bin("1011")="1101" report "bin 1011 must be gray 0101" severity failure;
assert gray2bin("1001")="1110" report "bin 1001 must be gray 0110" severity failure;
assert gray2bin("1000")="1111" report "bin 1000 must be gray 0111" severity failure;
wait;
end process test;
end architecture Testbench;
| bsd-3-clause |
richard42/CoCo3FPGA | T65.vhd | 1 | 15927 | -- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
P(Flag_B) <= '1';
end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
P(Flag_I) <= '1';
P(Flag_B) <= B_o;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;
| bsd-3-clause |
cathalmccabe/PYNQ | boards/ip/dvi2rgb_v1_7/src/TMDS_Clocking.vhd | 14 | 11908 | -------------------------------------------------------------------------------
--
-- File: TMDS_Clocking.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 10 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
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-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
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-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary primitives to obtain a fast
-- serial clock from the TMDS Clock pins to be used for deserializing the TMDS
-- Data channels. Connect this module directly to the top-level TMDS Clock pins
-- and a 200/300 MHz reference clock.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity TMDS_Clocking is
Generic (
kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
Port (
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
RefClk : in std_logic; -- 200MHz reference clock for IDELAY primitives; independent of DVI_Clk!
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
SerialClk : out std_logic;
PixelClk : out std_logic;
aLocked : out std_logic);
end TMDS_Clocking;
architecture Behavioral of TMDS_Clocking is
constant kDlyRstDelay : natural := 32;
signal aDlyLckd, rDlyRst, rBUFR_Rst, rLockLostRst : std_logic;
signal rDlyRstCnt : natural range 0 to kDlyRstDelay - 1 := kDlyRstDelay - 1;
signal clkfbout_hdmi_clk, CLK_IN_hdmi_clk, CLK_OUT_1x_hdmi_clk, CLK_OUT_5x_hdmi_clk : std_logic;
signal clkout1b_unused, clkout2_unused, clkout2b_unused, clkout3_unused, clkout3b_unused, clkout4_unused, clkout5_unused, clkout6_unused,
drdy_unused, psdone_unused, clkfbstopped_unused, clkinstopped_unused, clkfboutb_unused, clkout0b_unused, clkout1_unused : std_logic;
signal do_unused : std_logic_vector(15 downto 0);
signal LOCKED_int, rRdyRst : std_logic;
signal aMMCM_Locked, rMMCM_Locked_ms, rMMCM_Locked, rMMCM_LckdFallingFlag, rMMCM_LckdRisingFlag : std_logic;
signal rMMCM_Reset_q : std_logic_vector(1 downto 0);
signal rMMCM_Locked_q : std_logic_vector(1 downto 0);
begin
-- We need a reset bridge to use the asynchronous aRst signal to reset our circuitry
-- and decrease the chance of metastability. The signal rLockLostRst can be used as
-- asynchronous reset for any flip-flop in the RefClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aRst,
OutClk => RefClk,
oRst => rLockLostRst);
--IDELAYCTRL must be reset after configuration or refclk lost for 52ns(K7), 72ns(A7) at least
ResetIDELAYCTRL: process(rLockLostRst, RefClk)
begin
if Rising_Edge(RefClk) then
if (rLockLostRst = '1') then
rDlyRstCnt <= kDlyRstDelay - 1;
rDlyRst <= '1';
elsif (rDlyRstCnt /= 0) then
rDlyRstCnt <= rDlyRstCnt - 1;
else
rDlyRst <= '0';
end if;
end if;
end process;
IDelayCtrlX: IDELAYCTRL
port map (
RDY => aDlyLckd,
REFCLK => RefClk,
RST => rDlyRst);
RdyLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aDlyLckd,
OutClk => RefClk,
oRst => rRdyRst);
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "TMDS_33")
port map
(
O => CLK_IN_hdmi_clk,
I => TMDS_Clk_p,
IB => TMDS_Clk_n);
-- The TMDS Clk channel carries a character-rate frequency reference
-- In a single Clk period a whole character (10 bits) is transmitted
-- on each data channel. For deserialization of data channel a faster,
-- serial clock needs to be generated. In 7-series architecture an
-- ISERDESE2 primitive doing a 10:1 deserialization in DDR mode needs
-- a fast 5x clock and a slow 1x clock. These two clocks are generated
-- below with an MMCME2_ADV and BUFR primitive.
-- Caveats:
-- 1. The primitive uses a multiply-by-5 and divide-by-1 to generate
-- a 5x fast clock.
-- While changes in the frequency of the TMDS Clk are tracked by the
-- MMCM, for some TMDS Clk frequencies the datasheet specs for the VCO
-- frequency limits are not met. In other words, there is no single
-- set of MMCM multiply and divide values that can work for the whole
-- range of resolutions and pixel clock frequencies.
-- For example: MMCM_FVCOMIN = 600 MHz
-- MMCM_FVCOMAX = 1200 MHz for Artix-7 -1 speed grade
-- while FVCO = FIN * MULT_F
-- The TMDS Clk for 720p resolution in 74.25 MHz
-- FVCO = 74.25 * 10 = 742.5 MHz, which is between FVCOMIN and FVCOMAX
-- However, the TMDS Clk for 1080p resolution in 148.5 MHz
-- FVCO = 148.5 * 10 = 1480 MHZ, which is above FVCOMAX
-- In the latter case, MULT_F = 5, DIVIDE_F = 5, DIVIDE = 1 would result
-- in a correct VCO frequency, while still generating 5x and 1x clocks
-- 2. The MMCM+BUFIO+BUFR combination results in the highest possible
-- frequencies. PLLE2_ADV could work only with BUFGs, which limits
-- the maximum achievable frequency. The reason is that only the MMCM
-- has dedicated route to BUFIO.
-- If a PLLE2_ADV with BUFGs are used a second CLKOUTx can be used to
-- generate the 1x clock.
DVI_ClkGenerator: MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => real(kClkRange) * 5.0,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => real(kClkRange) * 1.0,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => real(kClkRange) * 6.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_hdmi_clk,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => CLK_OUT_5x_hdmi_clk,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_hdmi_clk,
CLKIN1 => CLK_IN_hdmi_clk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => aMMCM_Locked,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => rMMCM_Reset_q(0));
-- 5x fast serial clock
SerialClkBuffer: BUFIO
port map (
O => SerialClk, -- 1-bit output: Clock output (connect to I/O clock loads).
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);
-- 1x slow parallel clock
PixelClkBuffer: BUFR
generic map (
BUFR_DIVIDE => "5", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8"
SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES"
)
port map (
O => PixelClk, -- 1-bit output: Clock output port
CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only)
CLR => rBUFR_Rst, -- 1-bit input: Active high, asynchronous clear (Divided modes only)
I => CLK_OUT_5x_hdmi_clk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect
);
rBUFR_Rst <= rMMCM_LckdRisingFlag; --pulse CLR on BUFR one the clock returns
MMCM_Reset: process(rLockLostRst, RefClk)
begin
if (rLockLostRst = '1') then
rMMCM_Reset_q <= (others => '1'); -- MMCM_RSTMINPULSE Minimum Reset Pulse Width 5.00ns = two RefClk periods min
elsif Rising_Edge(RefClk) then
if (rMMCM_LckdFallingFlag = '1') then
rMMCM_Reset_q <= (others => '1');
else
rMMCM_Reset_q <= '0' & rMMCM_Reset_q(rMMCM_Reset_q'high downto 1);
end if;
end if;
end process MMCM_Reset;
MMCM_LockSync: entity work.SyncAsync
port map (
aReset => '0',
aIn => aMMCM_Locked,
OutClk => RefClk,
oOut => rMMCM_Locked);
MMCM_LockedDetect: process(RefClk)
begin
if Rising_Edge(RefClk) then
rMMCM_Locked_q <= rMMCM_Locked & rMMCM_Locked_q(1);
rMMCM_LckdFallingFlag <= rMMCM_Locked_q(1) and not rMMCM_Locked;
rMMCM_LckdRisingFlag <= not rMMCM_Locked_q(1) and rMMCM_Locked;
end if;
end process MMCM_LockedDetect;
GlitchFreeLocked: process(rRdyRst, RefClk)
begin
if (rRdyRst = '1') then
aLocked <= '0';
elsif Rising_Edge(RefClk) then
aLocked <= rMMCM_Locked_q(0);
end if;
end process GlitchFreeLocked;
end Behavioral;
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